Semiconductor device
View Patent ↗The semiconductor device includes a power element which is in an on state when voltage is not applied to a gate, a switching field-effect transistor for applying first voltage to the gate of the power element, and a switching field-effect transistor for applying voltage lower than the first voltage to the gate of the power element. The switching field-effect transistors have small off-state current.
1. A semiconductor device comprising:
a first voltage generation source;
a first transistor comprising a first gate, a first terminal connected to the first voltage generation source, and a second terminal;
a second transistor comprising a second gate, a third terminal connected to the second terminal, and a fourth terminal;
a power element comprising a third transistor comprising a third gate connected to the second terminal and the third terminal, a fifth terminal, and a sixth terminal;
a fourth transistor comprising a fourth gate, a seventh terminal connected to the fourth terminal, and a eighth terminal; and
a second voltage generation source connected to the eighth terminal;
a capacitor connected to the fourth terminal and the seventh terminal,
wherein the power element is provided so that current flows between the fifth terminal and the sixth terminal when voltage is not applied to the third gate.
2. The semiconductor device according to claim 1 , wherein the third transistor further comprises a fifth gate connected to the second terminal, the third terminal, and the third gate.
3. The semiconductor device according to claim 1 ,
wherein the first voltage generation source is a positive voltage generation source, and
wherein the second voltage generation source is a negative voltage generation source.
4. The semiconductor device according to claim 1 ,
wherein the first voltage generation source is a negative voltage generation circuit, and
wherein the second voltage generation source is a positive voltage generation circuit.
5. The semiconductor device according to claim 1 , wherein current does not flow in each of the first transistor, the second transistor, and the fourth transistor when voltage is not applied to each of the first gate, the second gate, and the fourth gate, respectively.
6. The semiconductor device according to claim 1 , wherein the third transistor comprises:
the third gate;
a first insulating layer over the third gate;
an oxide semiconductor layer over the first insulating layer; and
the fifth terminal and the sixth terminal over the oxide semiconductor layer.
7. The semiconductor device according to claim 6 , wherein the third transistor further comprises:
a second insulating layer over the fifth terminal and the sixth terminal, and
a fifth gate over the third gate with the second insulating layer interposed therebetween.
8. The semiconductor device according to claim 7 , wherein the fifth gate partly overlaps the fifth terminal and does not overlap the sixth terminal.
9. The semiconductor device according to claim 7 , wherein the fifth gate does not overlap the fifth terminal and the sixth terminal.
10. The semiconductor device according to claim 1 , wherein the third transistor comprises:
the fifth terminal;
an oxide semiconductor layer over the fifth terminal;
the sixth terminal over the oxide semiconductor layer;
an insulating layer over the sixth terminal; and
the third gate over the insulating layer,
wherein the third gate is provided in a region between the fifth terminal and the sixth terminal.
11. The semiconductor device according to claim 1 , wherein the third transistor comprises:
the fifth terminal;
an oxide semiconductor layer over the fifth terminal;
the sixth terminal over the oxide semiconductor layer;
an insulating layer over the sixth terminal; and
the third gate over the insulating layer,
wherein the third gate is provided in a region between the fifth terminal and the sixth terminal.
12. A semiconductor device comprising:
a first voltage generation source;
a first transistor comprising a first gate, a first terminal connected to the first voltage generation source, and a second terminal;
a second transistor comprising a second gate, a third terminal connected to the second terminal, and a fourth terminal;
a power element comprising a third transistor comprising a third gate connected to the second terminal and the third terminal, a fifth terminal, and a sixth terminal; and
a second voltage generation source connected to the fourth terminal;
an overvoltage detection circuit connected to the first gate and the second gate,
wherein the power element is provided so that current flows between the fifth terminal and the sixth terminal when voltage is not applied to the third gate.
13. The semiconductor device according to claim 12 , wherein the third transistor further comprises a fourth gate connected to the second terminal, the third terminal, and the third gate.
14. The semiconductor device according to claim 12 , further comprising:
a fourth transistor comprising a fourth gate, a seventh terminal, and an eighth terminal; and
a capacitor,
wherein the seventh terminal is connected to the fourth terminal and the capacitor,
wherein the eighth terminal is connected to the second voltage generation source, and
wherein the fourth terminal is connected to the second voltage generation source through the fourth transistor.
15. The semiconductor device according to claim 12 ,
wherein the first voltage generation source is a positive voltage generation source, and
wherein the second voltage generation source is a negative voltage generation source.
16. The semiconductor device according to claim 12 ,
wherein the first voltage generation source is a negative voltage generation circuit, and
wherein the second voltage generation source is a positive voltage generation circuit.
17. The semiconductor device according to claim 12 , further comprising an inverter,
wherein the second gate is connected to the overvoltage detection circuit through the inverter.
18. The semiconductor device according to claim 12 , wherein current does not flow in each of the first transistor and the second transistor when voltage is not applied to each of the first gate and the second gate, respectively.
19. The semiconductor device according to claim 12 , wherein the third transistor comprises:
the third gate;
a first insulating layer over the third gate;
an oxide semiconductor layer over the first insulating layer; and
the fifth terminal and the sixth terminal over the oxide semiconductor layer.
20. The semiconductor device according to claim 19 , wherein the third transistor further comprises:
a second insulating layer over the fifth terminal and the sixth terminal, and
a fifth gate over the third gate with the second insulating layer interposed therebetween.
21. The semiconductor device according to claim 20 , wherein the fifth gate partly overlaps the fifth terminal and does not overlap the sixth terminal.
22. The semiconductor device according to claim 20 , wherein the fifth gate does not overlap the fifth terminal and the sixth terminal.
23. The semiconductor device according to claim 12 , wherein the third transistor comprises:
the fifth terminal;
an oxide semiconductor layer over the fifth terminal;
the sixth terminal over the oxide semiconductor layer;
an insulating layer over the sixth terminal; and
the third gate over the insulating layer,
wherein the third gate is provided in a region between the fifth terminal and the sixth terminal.
24. A semiconductor device comprising:
a first voltage generation source;
a first transistor comprising a first gate, a first terminal connected to the first voltage generation source, and a second terminal;
a second transistor comprising a second gate, a third terminal connected to the second terminal, and a fourth terminal;
a power element comprising a third transistor comprising a third gate connected to the second terminal and the third terminal, a fifth terminal, and a sixth terminal;
a fourth transistor comprising a fourth gate, a seventh terminal connected to the fourth terminal, and an eighth terminal;
a capacitor connected to the fourth terminal and the seventh terminal;
a second voltage generation source connected to the eighth terminal;
an overvoltage detection circuit connected to the first gate and the second gate; and
a refresh control circuit connected to the fourth gate,
wherein the power element is provided so that current flows between the fifth terminal and the sixth terminal when voltage is not applied to the third gate.
25. The semiconductor device according to claim 24 , wherein the third transistor further comprises a fifth gate connected to the second terminal, the third terminal, and the third gate.
26. The semiconductor device according to claim 24 ,
wherein the first voltage generation source is a positive voltage generation source, and
wherein the second voltage generation source is a negative voltage generation source.
27. The semiconductor device according to claim 24 ,
wherein the first voltage generation source is a negative voltage generation circuit, and
wherein the second voltage generation source is a positive voltage generation circuit.
28. The semiconductor device according to claim 24 , further comprising an inverter,
wherein the second gate is connected to the overvoltage detection circuit through the inverter.
29. The semiconductor device according to claim 24 , wherein current does not flow in each of the first transistor, the second transistor, and the fourth transistor when voltage is not applied to each of the first gate, the second gate, and the fourth gate, respectively.
30. The semiconductor device according to claim 24 , wherein the refresh control circuit comprises:
an oscillator circuit;
a divider circuit connected to the oscillator circuit;
a delay circuit connected to the divider circuit; and
an AND circuit comprising a first input terminal, a second input terminal, and an output terminal,
wherein the first input terminal is connected to the divider circuit,
wherein the second input terminal is connected to the delay circuit, and
wherein the output terminal is connected to the fourth gate.
31. The semiconductor device according to claim 24 , wherein the third transistor comprises:
the third gate;
a first insulating layer over the third gate;
an oxide semiconductor layer over the first insulating layer; and
the fifth terminal and the sixth terminal over the oxide semiconductor layer.
32. The semiconductor device according to claim 31 , wherein the third transistor further comprises:
a second insulating layer over the fifth terminal and the sixth terminal; and
a fifth gate over the third gate with the second insulating layer interposed therebetween.
33. The semiconductor device according to claim 32 , wherein the fifth gate partly overlaps the fifth terminal and does not overlap the sixth terminal.
34. The semiconductor device according to claim 32 , wherein the fifth gate does not overlap the fifth terminal and the sixth terminal.