IP Library › Granted Patent US 8,349,711
Granted Patent B2
US 8,349,711 · App. 13/015,303 · Granted Jan 8, 2013

Single crystal group III nitride articles and method of producing same by HVPE method incorporating a polycrystalline layer for yield enhancement

Assignee: Kyma Technologies, Inc.
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Quick Facts
Patent No.
US 8,349,711
App. No.
13/015,303
Granted
Jan 8, 2013
Kind
B2
Abstract

In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article.

Claims (22)

1. A method of forming a semiconductor structure, the method comprising:

forming, over a substrate, a single-crystalline layer comprising a first III-nitride semiconductor material; and

forming, over the single-crystalline layer, a polycrystalline layer comprising a second III-nitride semiconductor material, thereby forming the semiconductor structure.

2. The method of claim 1 , wherein the first III-nitride semiconductor material and the second III-nitride semiconductor material are the same.

3. The method of claim 1 , wherein the substrate is selected from the group consisting of sapphire, silicon carbide, gallium arsenide, zinc oxide, silicon, spinel, lithium gallate, and lithium aluminate.

4. The method of claim 1 , further comprising, prior to forming the single-crystalline layer, forming an epitaxial nitride layer over the substrate.

5. The method of claim 4 , wherein the epitaxial nitride layer comprises a material selected from the group consisting of GaN, AlN, InN, and ternary and quaternary alloys and mixtures including one or more thereof.

6. The method of claim 4 , wherein forming the epitaxial nitride layer comprises sputtering.

7. The method of claim 1 , wherein forming the single-crystalline layer comprises:

forming a nucleation layer over the substrate under a substantially three-dimensional growth mode; and

forming a bulk layer over the nucleation layer under a substantially two-dimensional growth mode.

8. The method of claim 7 , wherein the nucleation layer and the bulk layer each comprise a material selected from the group consisting of GaN, AlN, InN, and ternary and quaternary alloys and mixtures including one or more thereof.

9. The method of claim 7 , wherein forming the single-crystalline layer comprises forming, between the nucleation layer and the bulk layer, a transitional layer under a growth mode that changes from the substantially three-dimensional growth mode to the substantially two-dimensional growth mode.

10. The method of claim 9 , wherein the transitional layer comprises a material selected from the group consisting of GaN, AlN, InN, and ternary and quaternary alloys and mixtures including one or more thereof.

11. The method of claim 1 , wherein the second III-nitride semiconductor material comprises a material selected from the group consisting of GaN, AlN, InN, and ternary and quaternary alloys and mixtures including one or more thereof.

12. The method of claim 1 , wherein forming the single-crystalline layer comprises doping with at least one of an n-type dopant, a p-type dopant, or a deep-level acceptor.

13. The method of claim 1 , wherein the polycrystalline layer is formed at an elevated temperature greater than approximately 850° C., and further comprising cooling the semiconductor structure from the elevated temperature.

14. The method of claim 13 , wherein the substrate separates from at least a portion of the single-crystalline layer during cooling.

15. The method of claim 13 , wherein the semiconductor structure is cooled at a rate less than approximately 20° C. per minute.

16. The method of claim 1 , further comprising removing the polycrystalline layer from the single-crystalline layer.

17. The method of claim 16 , wherein removing the polycrystalline layer comprises at least one of grinding, lapping, or polishing.

18. The method of claim 16 , further comprising processing the single-crystalline layer by at least one of planarization, polishing, chemical-mechanical polishing, grinding or lapping.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 10, 2011
From: PREBLE, EDWARD A.; LIU, LIANGHONG; HANSER, ANDREW D.; WILLIAMS, N. MARK; XU, XUEPING
To: KYMA TECHNOLOGIES, INC.
Reel/Frame 025787/0886 →
Continuity (7)
Continuation 11606783 · Nov 30, 2006
Provisional Application 60749728 · Dec 12, 2005
Provisional Application 60750982 · Dec 16, 2005
Provisional Application 60810537 · Jun 2, 2006
Provisional Application 60843036 · Sep 8, 2006
Provisional Application 60847855 · Sep 28, 2006
Related Publication 20110198590A1 · Aug 18, 2011