Precise resistor on a semiconductor device

1. A method of making an integrated circuit, the method comprising:

forming a polysilicon layer on a substrate;

patterning the polysilicon layer to form a polysilicon resistor and a polysilicon gate;

forming a protective layer over the polysilicon gate;

performing a first ion implantation to the polysilicon layer to adjust electric resistance of the polysilicon resistor, wherein the polysilicon gate is covered by the protective layer during performance of the first ion implantation;

performing a second ion implantation to a top portion of the polysilicon resistor such that the top portion has an enhanced etch resistance; and

performing an etch process to remove the polysilicon gate while the polysilicon resistor is protected by the implanted top portion.

2. The method of claim 1 , further comprising forming a high-k dielectric material layer on the substrate.

3. The method of claim 1 , wherein the performing the second ion implantation includes implanting the polysilicon resistor using one of boron (B) and boron fluoride (BF2).

4. The method of claim 1 , wherein the performing the first ion implantation includes implanting the polysilicon resistor using one of BF2 and B.

5. The method of claim 1 , wherein the performing the second ion implantation includes implanting doping species to the top portion having a thickness less than about 5 nm.

6. The method of claim 5 , wherein the top portion of the polysilicon resistor includes boron as dopant with a doping concentration greater than about 10 19 /cm 3 .

7. The method of claim 1 , further comprising:

forming source and drain in the substrate and interposed by the polysilicon gate;

forming a metal layer in a gate trench formed after the performing an etch process;

filling the gate trench with a conductive layer on the metal layer; and

performing a chemical mechanical polishing process to remove excessive portions of the metal layer and the conductive layer.

8. The method of claim 7 , wherein the source and drain are n-type dopant, and the metal layer has a work function less than 4.2 eV.

9. The method of claim 7 , wherein the source and drain are p-type dopant, the metal layer has a work function greater than 5.2 eV.

10. The method of claim 1 , wherein the performing a first ion implantation to the polysilicon layer includes performing the first ion implantation to the polysilicon layer before the patterning the polysilicon layer.

11. The method of claim 1 , further comprising, after the performing a second ion implantation and before the performing an etch process:

forming an inter-level dielectric (ILD) layer on the semiconductor substrate; and

performing a first chemical mechanical polishing process to etch back the ILD layer.

12. A method comprising:

forming a polysilicon resistor and a polysilicon gate on a semiconductor substrate;

performing a first ion implantation to the polysilicon resistor to adjust electric resistance of the polysilicon resistor, wherein the polysilicon gate is covered by a first patterned material layer during performance of the first ion implantation;

performing a second ion implantation to the polysilicon gate to form source and drain regions in the semiconductor substrate that are adjacent the polysilicon gate, wherein the polysilicon resistor is covered by a second patterned material layer during performance of the second ion implantation; and

performing a third ion implantation to the polysilicon resistor such that a top portion of the polysilicon resistor has an enhanced etch resistance, wherein the polysilicon gate is covered by a third patterned material layer during performance of the third ion implantation.

13. The method of claim 12 , wherein the first, second, and third material layers are different from each other.

14. The method of claim 12 , wherein the first, second, and third ion implantations are different from each other.

15. The method of claim 12 , wherein performing the first ion implantation includes implanting the polysilicon resistor using boron (B) and wherein performing the first ion implantation includes implanting the polysilicon resistor using boron fluoride (BF2).

16. The method of claim 12 , wherein performing the second ion implantation to the polysilicon gate to form source and drain regions in the semiconductor substrate that are adjacent the polysilicon gate occurs after performing the first ion implantation and before performing the third ion implantation.

17. The method of claim 12 , further comprising removing the first patterned material layer covering the polysilicon gate prior to performing the third ion implantation.

18. The method of claim 12 , performing an etch process to remove the polysilicon gate while the polysilicon resistor is protected by the implanted top portion.

19. A method comprising:

forming a polysilicon resistor and a polysilicon gate on a semiconductor substrate;

forming a first patterned material layer over the polysilicon gate;

performing a first ion implantation to the polysilicon resistor to adjust electric resistance of the polysilicon resistor, wherein the polysilicon gate is covered by the first patterned material layer during performance of the first ion implantation;

forming a second patterned material layer over the polysilicon gate, the second patterned material layer being different than the first patterned material layer; and

after forming the second patterned material layer over the polysilicon gate, performing a second ion implantation to the polysilicon resistor such that a top portion of the polysilicon resistor has an enhanced etch resistance, wherein the polysilicon gate is covered by the second patterned material layer during performance of the second ion implantation.

20. The method of claim 19 , further comprising removing the first patterned material layer prior to performing the second ion implantation.