Stepped-source LDMOS architecture
A semiconductor device can include a source region near a working top surface of a semiconductor region. The device can also include a gate located above the working top surface and located laterally between the source and a drain region. The source region and the gate can at least partially laterally overlap a body region near the working top surface. The source region can include a first portion having the first conductivity type, a second portion having a second conductivity type, and a third portion having the second conductivity type. The second portion can be located laterally between the first and third portions and can penetrate into the semiconductor region to a greater depth than the third portion but no more than the first portion. The lateral location of the third portion can be determined at least in part using the lateral location of the gate.
1. A semiconductor device, comprising:
a source region near a working top surface of a semiconductor region;
a drain region near the working top surface and laterally offset from the source region;
a gate located above the working top surface and located laterally between the source and drain regions; and
wherein the source region and the gate at least partially laterally overlap a body region near the working top surface;
wherein the semiconductor region comprises a first conductivity type having a first doping profile; and
wherein the body region comprises the first conductivity type having a second doping profile;
wherein the source region comprises:
a first portion having the first conductivity type having a third doping profile, a second portion having a second conductivity type having a fourth doping profile, and a third portion having the second conductivity type having a fifth doping profile;
wherein the second portion is located laterally between the first and third portions and penetrates into the semiconductor region to a greater depth than the third portion but no more than the first portion; and
wherein the lateral location of the third portion is determined at least in part using the lateral location of the gate.
2. The semiconductor device of claim 1 , wherein the semiconductor region includes a semiconductor substrate.
3. The semiconductor device of claim 1 , wherein the first conductivity type is n type and the second conductivity type is p type.
4. The semiconductor device of claim 1 , wherein the fourth doping profile corresponds to the fifth doping profile.
5. The semiconductor device of claim 1 , wherein a third doping profile peak concentration is greater than a second doping profile peak concentration.
6. The semiconductor device of claim 5 , wherein the third doping profile is more highly doped with respect to the first doping profile and the second doping profile.
7. The semiconductor device of claim 1 , wherein the gate includes a polysilicon portion and a first oxide spacer at the lateral edge of the gate near the source region, and wherein the lateral location of the third portion of the source region is determined at least in part using the lateral location of the first oxide spacer.
8. The semiconductor device of claim 7 , wherein a channel length of the gate along the working top surface is determined at least in part by the width of the first oxide spacer and the lateral location of the third portion of the source region.
9. The semiconductor device of claim 7 , wherein the width of the polysilicon portion includes a tapered portion and gets narrower near the working top surface of the semiconductor region.
10. The semiconductor device of claim 7 , wherein the gate includes a second oxide spacer extending laterally from the first oxide spacer, and wherein the lateral location of the second portion of the source region is determined at least in part using the lateral location of the second oxide spacer.
11. The semiconductor device of claim 10 , wherein a gate-to-source capacitance (Cgs) is controlled at least in part using a lateral thickness of at least one of the first or second oxide spacers.
12. The semiconductor device of claim 10 , comprising:
a first silicide region above the first and second portions of the source region;
a second silicide region on top of the gate; and
wherein the lateral location of the first silicide region is determined at least in part using the second oxide spacer.
13. The semiconductor device of claim 1 , wherein the semiconductor region comprises a well region having the first conductivity type within a semiconductor substrate having the second conductivity type.
14. The semiconductor device of claim 1 , wherein the body region at least partially surrounds the first, second, and third portions of the source region.
15. The semiconductor device of claim 14 , wherein the body region penetrates into the semiconductor region to a depth greater than the first, second, and third portions of the source region.
16. The semiconductor device of claim 1 , comprising a drift region located laterally between the gate and the drain region and at least partially overlapping with the gate and drain regions, and wherein the drift region includes the second conductivity type.
17. The semiconductor device of claim 16 , wherein the drain region includes the second conductivity type having a sixth doping profile, and wherein a peak doping concentration of the sixth doping profile is greater than a peak doping concentration of a drift region doping profile.
18. The semiconductor device of claim 16 , wherein the drift region includes a shallow portion including the second conductivity type having a peak doping concentration greater than an average drift region doping concentration, wherein the shallow portion extends laterally from the drain region toward the gate.
19. The semiconductor device of claim 18 , wherein the gate includes a polysilicon portion and a first oxide spacer at the lateral edge of the gate, wherein the lateral location of an upper portion of the shallow portion of the drift region near the first oxide spacer is determined at least in part by the location of the first oxide spacer, and wherein the shallow portion includes a lower portion extending further under the lateral edge of the gate than the upper portion.
20. The semiconductor device of claim 19 , wherein a difference between the lateral position of the upper and lower portions of the shallow portion of the drift region is determined at least in part by boron segregation and configured to increase a drain-to-source breakdown voltage when the semiconductor device is in an off-state.
21. The semiconductor device of claim 18 , wherein the drift region comprises a deep portion located at a greater depth within the semiconductor region than the shallow region, the deep portion including the second conductivity type having a peak doping concentration less than the average drift region doping concentration, wherein the deep portion extends laterally from the drain region toward the gate but not as far as the shallow portion, and wherein the shallow and deep portions are vertically separated along at least a portion of their overlapping width by a region of the first conductivity type in the lateral region extending from the gate toward the drain region.
22. A semiconductor device, comprising:
a source region near a working top surface of a semiconductor region;
a drain region near the working top surface and laterally offset from the source region;
a gate located above the working top surface and located laterally between the source and drain regions; and
wherein the source region and the gate at least partially laterally overlap a body region near the working top surface;
wherein the semiconductor region comprises a first conductivity type having a first doping profile;
wherein the body region comprises the first conductivity type having a second doping profile;
wherein the source region comprises:
a first portion having the first conductivity type having a third doping profile, a second portion having a second conductivity type having a fourth doping profile, and a third portion having the second conductivity type having a fifth doping profile;
wherein the second portion is located laterally between the first and third portions and penetrates into the semiconductor region to a greater depth than the third portion but no more than the first portion; and
wherein the lateral location of the third portion is determined at least in part using the lateral location of the gate;
wherein the fourth doping profile corresponds to the fifth doping profile;
wherein a third doping profile peak concentration is greater than a second doping profile peak concentration;
wherein the first conductivity type is n type and the second conductivity type is p type; and
wherein the gate includes a polysilicon portion and a first oxide spacer at the lateral edge of the gate near the source region, and wherein the lateral location of the third portion of the source region is determined at least in part using the lateral location of the first oxide spacer.
23. The semiconductor device of claim 22 , wherein the gate includes a second oxide spacer extending laterally from the first oxide spacer, and wherein the lateral location of the second portion of the source region is determined at least in part using the lateral location of the second oxide spacer.