Soft-error detection for electronic-circuit registers
In one embodiment, a circuit has multiple flip-flops with gated clock inputs controlled by an enable signal, where the clock signal is gated in order to reduce power consumption by the circuit. The circuit has an error detection and correction (EDC) module that is active when the enable signal is low in order to detect and correct soft errors of the flip-flops. The EDC module generates and stores an error-correction code based on the data outputs of the flip-flops. The EDC module then compares the stored error-correction code to a presently generated error-correction code, where if they are not identical, then the EDC (a) determines (i) that a soft error has occurred and (ii) which flip-flop suffered the soft error and (b) flips a corresponding error-correction signal to provide a correct corresponding output signal while the enable signal is low.
1. An integrated circuit comprising:
a first plurality of flip-flops, each flip-flop adapted to:
receive a corresponding data-input signal and a corresponding clock-input signal;
provide a corresponding data-output signal; and
use less energy when the corresponding clock-input signal is constant than when the corresponding clock-input signal is not constant; and
an error-detection module connected to receive the data-output signals of the first plurality of flip-flops, wherein the error-detection module is adapted to:
generate a first error-detection code based on a first set of values of the received data-output signals of the first plurality of flip-flops; and
process (i) the first error-detection code and (ii) a second set of values of the received data-output signals of the first plurality of flip-flops to generate an error-detection signal indicating whether or not the error-detection module detected a soft error of a flip-flop in the second set of values of the received data-output signals.
2. The integrated circuit of claim 1 , wherein the error-detection module is adapted to generate the error-detection signal by:
generating a second error-detection code based on the second set of values of the received data-output signals of the first plurality of flip-flops; and
comparing the first error-detection code to the second error-detection code to generate the error-detection signal.
3. The integrated circuit of claim 2 , wherein the error-detection module determines whether the second error-detection code is identical to the first error-detection code.
4. The integrated circuit of claim 2 , wherein the integrated circuit further comprises a bit comparator adapted to perform the comparison of the first error-detection code to the second error-detection code and generate the error-detection signal based on the comparison.
5. The integrated circuit of claim 1 , wherein the integrated circuit further comprises a first gate module adapted to:
receive a clock signal and an enable signal;
generate an output signal that (1) follows the received clock signal, when the received enable signal has a first value, and (2) remains at a second value when the received enable signal has a third value different from the first value; and
provide the output signal to one or more flip-flops of the first plurality of flip-flops, wherein the output signal corresponds to the clock-input signals of the one or more flip-flops of the first plurality of flip-flops.
6. The integrated circuit of claim 5 , wherein the first gate module's output signal corresponds to the clock-input signal of all of the flip-flops of the first plurality of flip-flops.
7. The integrated circuit of claim 5 , wherein the error-detection module is adapted to store the first error-detection code in response to the enable signal transitioning from the first value to the third value.
8. The integrated circuit of claim 7 , wherein, while the received enable signal has the third value, the error-detection module is adapted to update the error detection signal based on (i) the first error-detection code and (ii) an updated second set of values of the received data-output signals of the first plurality of flip-flops.
9. The integrated circuit of claim 5 , further comprising synchronous-disable circuitry connected to provide to the error-detection module a latched enable signal that is based on the enable signal and the clock signal, such that:
if the enable signal transitions from a fourth value to a fifth value, then the latched enable signal consequently transitions from a corresponding sixth value to a corresponding seventh value; and
if the enable signal transitions from the fifth value to the fourth value, then the latched enable signal subsequently transitions from the corresponding seventh value to the corresponding sixth value at a time dependent on the clock signal.
10. The integrated circuit of claim 1 , wherein the first plurality of flip-flops comprises a first flip-flop and a second flip-flop, wherein the data input signal of the first flip-flop is independent of the data input signal of the second flip-flop.
11. The integrated circuit of claim 1 , wherein the integrated circuit further comprises a controller adapted to receive the error-detection signal and perform a corrective action in response to the error-detection signal indicating that the error-detection module detected the soft error of the flip-flop in the second set of values of the received data-output signals.
12. The integrated circuit of claim 1 , wherein the controller is adapted to perform the corrective action by refreshing the first plurality of flip-flops.
13. The integrated circuit of claim 1 , wherein:
the error-detection module is an error detection and correction module;
the first error-detection code is an error-correction code; and
the error detection and correction module is further adapted to generate a plurality of error-correction signals whose values are based on the first error-detection code and the second set of values of the received data-output signals of the first plurality of flip-flops, wherein the plurality of error-correction signals are used to compensate for the soft error of the flip-flop.
14. The integrated circuit of claim 13 , wherein:
each error-correction signal corresponds to a different flip-flop of the first plurality of flip-flops;
the integrated circuit further comprises an error-correcting gate module for each flip-flop of the first plurality of flip-flops;
each error-correcting gate module is connected to receive (i) the data-output signal of the corresponding flip-flop and (ii) the corresponding error-correction signal; and
each error-correcting gate module is adapted to output (i) the data-output signal of the corresponding flip-flop when the corresponding error-correction signal indicates that the error detection and correction module did not detect a soft error of the corresponding flip-flop and (ii) the inverse of the data-output signal of the corresponding flip-flop when the corresponding error-correction signal indicates that the error detection and correction module detected a soft error of the corresponding flip-flop.
15. The integrated circuit of claim 1 , wherein:
(a) the error-detection module is adapted to generate the error-detection signal by:
(1) generating a second error-detection code based on the second set of values of the received data-output signals of the first plurality of flip-flops; and
(2) comparing the first error-detection code to the second error-detection code to generate the error-detection signal;
(b) the integrated circuit further comprises:
(1) a first gate module adapted to:
receive a clock signal and an enable signal;
generate an output signal that (1) follows the received clock signal, when the received enable signal has a first value, and (2) remains at a second value when the received enable signal has a third value different from the first value; and
provide the output signal to one or more flip-flops of the first plurality of flip-flops, wherein the output signal corresponds to the clock-input signals of the one or more flip-flops of the first plurality of flip-flops;
(2) a bit comparator adapted to perform the comparison of the first error-detection code to the second error-detection code, when the enable signal has the third value, and generate the error-detection signal based on the comparison; and
(3) a controller adapted to receive the error-detection signal and perform a corrective action in response to the error-detection signal indicating that the error-detection module detected the soft error of the flip-flop in the second set of values of the received data-output signals;
(c) the first gate module's output signal corresponds to the clock-input signal of all of the flip-flops of the first plurality of flip-flops; and
(d) the error-detection module is adapted to store the first error-detection code in response to the enable signal transitioning from the first value to the third value.
16. The integrated circuit of claim 15 , wherein:
the error-detection module is an error detection and correction module;
the first error-detection code is a Hamming code based on the first set of values of the received data-output signals of the first plurality of flip-flops;
the error detection and correction module is further adapted to generate a plurality of error-correction signals whose values are based on the first error-detection code and the second set of values of the received data-output signals of the first plurality of flip-flops, wherein the plurality of error-correction signals are used to compensate for the soft error of the flip-flop;
each error-correction signal corresponds to a different flip-flop of the first plurality of flip-flops;
the integrated circuit further comprises an error-correcting gate module for each flip-flop of the first plurality of flip-flops;
each error-correcting gate module is connected to receive (i) the data-output signal of the corresponding flip-flop and (ii) the corresponding error-correction signal; and
each error-correcting gate module is adapted to output (i) the data-output signal of the corresponding flip-flop when the corresponding error-correction signal indicates that the error detection and correction module did not detect a soft error of the corresponding flip-flop and (ii) the inverse of the data-output signal of the corresponding flip-flop when the corresponding error-correction signal indicates that the error detection and correction module detected a soft error of the corresponding flip-flop.
17. A method for detecting a soft error of a flip-flop in a first plurality of flip-flops in an integrated circuit, the method comprising:
receiving, by each flip-flop of the first plurality of flip-flops, a corresponding data-input signal and a corresponding clock-input signal, wherein the flip-flop uses less energy when the corresponding clock-input signal is constant than when the corresponding clock-input signal is not constant;
providing, by each flip-flop of the first plurality of flip-flops, a corresponding data-output signal;
generating a first error-detection code based on a first set of values of the data-output signals of the first plurality of flip-flops; and
processing (i) the first error-detection code and (ii) a second set of values of the data-output signals of the first plurality of flip-flops to generate an error-detection signal indicating whether or not the soft error of the flip-flop was detected in the second set of values of the received data-output signals.
18. The method of claim 17 , wherein generating the error-detection signal comprises:
generating a second error-detection code based on the second set of values of the received data-output signals of the first plurality of flip-flops; and
comparing the first error-detection code to the second error-detection code to generate the error-detection signal.
19. The method of claim 17 , further comprising:
generating a gate-module output signal that (1) follows a received clock signal, when a received enable signal has a first value, and (2) remains at a second value when the received enable signal has a third value different from the first value;
providing the gate-module output signal to one or more flip-flops of the first plurality of flip-flops, wherein the gate-module output signal corresponds to the clock-input signals of the one or more flip-flops of the first plurality of flip-flops;
storing the first error-detection code in response to the received enable signal transitioning from the first value to the third value; and
performing a corrective action in response to the error-detection signal indicating that the soft error of the flip-flop was detected in the second set of values of the received data-output signals.
20. The method of claim 17 , further comprising:
generating a plurality of error-correction signals, each corresponding to a different flip-flop of the first plurality of flip-flops, whose values are based on the first error-detection code and the second set of values of the received data-output signals of the first plurality of flip-flops;
using the plurality of error-correction signals to compensate for the soft error of the flip-flop;
outputting (i) the data-output signal of the corresponding flip-flop when the corresponding error-correction signal indicates that the error detection and correction module did not detect a soft error of the corresponding flip-flop and (ii) the inverse of the data-output signal of the corresponding flip-flop when the corresponding error-correction signal indicates that the error detection and correction module detected a soft error of the corresponding flip-flop.
21. The integrated circuit of claim 1 , wherein:
the first set of values of the received data-output signals of the first plurality of flip-flops represents the outputs of the flip-flops at a first time;
the second set of values of the received data-output signals of the first plurality of flip-flops represents the outputs of the flip-flops at a second time that is later than the first time; and
the soft error, if any is detected, occurred between the first time and the second time.