IP Library Granted Patent US 8,383,489
Granted Patent B2
US 8,383,489 · App. 12/815,048 · Granted Feb 26, 2013

SOI wafer and method for forming the same

Inventor: Herb He Huang (Jiangsu Province, CN)
Assignee: Jiangsu Lexvu Electronics Co., Ltd.
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Quick Facts
Patent No.
US 8,383,489
App. No.
12/815,048
Granted
Feb 26, 2013
Kind
B2
Abstract

An SOI wafer and a method for forming the same, where the method for forming an SOI wafer includes: preparing a monocrystalline silicon wafer on which a mask layer is formed; etching the mask layer and the monocrystalline silicon wafer to form several trenches; forming a first insulating layer on the sidewalls and the bottoms of the trenches; etching and removing the first insulating layer on the bottoms of the trenches; etching along the trenches the monocrystalline silicon wafer beneath the trenches to form cavities; processing the inner walls of the cavities to form a second insulating layer; and filling up the trenches and the cavities with an insulating material layer. The process of the invention is easy to be implemented at a low manufacturing cost and an SOI wafer being formed is of high quality while being capable of being compatible with a standard process of manufacturing a bulk silicon CMOS.

Claims (22)

1. A method for forming an SOI wafer, comprising:

preparing a monocrystalline silicon wafer on which a mask layer is formed;

etching the mask layer and the monocrystalline silicon wafer to form several trenches;

forming a first insulating layer on the sidewalls and the bottoms of the trenches;

etching and removing the first insulating layer on the bottoms of the trenches;

etching along the trenches the monocrystalline silicon wafer beneath the trenches to form cavities;

processing the inner walls of the cavities to form a second insulating layer, the second insulating layers in adjacent cavities connecting with each other to split the monocrystalline silicon wafer into an upper sector of a top layer silicon and a lower sector of a silicon substrate; and

filling up the trenches and the cavities with an insulating material layer.

2. The method for forming an SOI wafer according to claim 1 , wherein the mask layer comprises a first film layer and a second film layer on the first film layer.

3. The method for forming an SOI wafer according to claim 2 , wherein the first film layer is made of silicon oxide, and the second film layer is made of silicon nitride.

4. The method for forming an SOI wafer according to claim 1 , wherein the first insulating layer is formed through thermal oxidization, thermal nitrification or chemical vapor deposition.

5. The method for forming an SOI wafer according to claim 4 , wherein the first insulating layer is made of silicon oxide or silicon nitride with a thickness of 1 nm to 10 μm.

6. The method for forming an SOI wafer according to claim 1 , wherein the first insulating layer on the bottoms is etched and removed through plasma etching or ion beam etching using Gas of Argon.

7. The method for forming an SOI wafer according to claim 1 , wherein the monocrystalline silicon wafer is etched through dry etching using gas of XeF2 or mixed gas of HNO3 and HF.

8. The method for forming an SOI wafer according to claim 1 , wherein the second insulating layer is formed through thermal oxidation or thermal nitrification.

9. The method for forming an SOI wafer according to claim 8 , wherein the second insulating layer is made of silicon oxide or silicon nitride.

10. The method for forming an SOI wafer according to claim 1 , wherein the insulating material layer is filled through low-pressure chemical vapor disposition or spin coating.

11. The method for forming an SOI wafer according to claim 10 , wherein the insulating material layer is made of silicon oxide or silicon oxide containing phosphor, boron, carbon, nitrogen or hydrogen.

12. The method for forming an SOI wafer according to claim 1 , wherein the number of the trenches is dependent upon whether the cavities to be formed subsequently beneath the trenches can be interconnected to separate the monocrystalline silicon wafer into a silicon substrate and a top layer of silicon.

13. The method for forming an SOI wafer according to claim 1 , wherein the cavities are spaced at an interval of approximately 10 nm to 1000 nm, and the monocrystalline silicon at the interval is processed to form a part of the second insulating layer in the following processing step.

14. The method for forming an SOI wafer according to claim 1 , wherein the adjacent cavities are interconnected with each other completely.

15. The method for forming an SOI wafer according to claim 1 , wherein the cavities having a depth of 50 nm to 50 um arranged in the monocrystialline silicon wafer.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 21, 2016
From: ZHENJIANG XINNA MICROELECTRONICS CO., LTD.
To: XI'AN YISHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
Reel/Frame 038055/0921 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 14, 2016
From: JIANGSU LEXVU ELECTRONICS CO., LTD.
To: XI'AN YISHEN OPTOELECTRONICS TECHNOLOGY CO., LTD.
Reel/Frame 037970/0307 →
CHANGE OF NAME Recorded Mar 4, 2016
From: JIANGSU LEXVU ELECTRONICS CO., LTD.
To: ZHENJIANG XINNA MICROELECTRONICS CO., LTD.
Reel/Frame 038001/0634 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 14, 2010
From: HUANG, HERB HE
To: JIANGSU LEXVU ELECTRONICS CO., LTD.
Reel/Frame 024532/0444 →
Priority Claims (1)
CN 2009 1 0165230 · Aug 13, 2009 · national
Continuity (1)
Related Publication 20110037142A1 · Feb 17, 2011