Flash cell with floating gate transistors formed using spacer technology
Methods for forming split gate flash cell structures provide for symmetrical cells that are immune to misalignment of the photoresist pattern when forming the control gates. Spacers are utilized to form the floating gates in the floating gate transistors used in the flash cells. The spacers may be oxide spacers used to mask a polysilicon layer that will form the floating gates or the spacers may be polysilicon spacers that will themselves form the floating gates. The inter-gate oxide of the floating gate transistors may be formed using HTO or may be deposited. Hard mask spacers are used in conjunction with the control gate photoresist patterning operation to control the size and configuration of the control gate and the channel length.
1. A method for forming a split gate flash cell comprising:
forming segments of a sacrificial film over a substrate, said segments bounded by sidewalls;
depositing a polysilicon layer covering and interposed between said segments;
depositing an oxide over said polysilicon layer;
anisotropically etching said oxide to produce spacers therefrom, said spacers disposed adjacent vertical portions of said polysilicon layer that are adjacent said sidewalls;
using said spacers as masks and anisotropically etching said polysilicon layer to form polysilicon segments therefrom, each said polysilicon segment including a vertical part and a horizontal part; and
forming floating gate transistors using said polysilicon segments as said floating gates.
2. The method as in claim 1 , wherein said forming segments of a sacrificial film comprise forming said sacrificial film over said substrate and patterning said sacrificial film to form said segments therefrom.
3. The method as in claim 1 , wherein said sacrificial film comprises silicon nitride.
4. The method as in claim 1 , wherein said anisotropically etching said oxide includes producing said spacers such that said spacers cover horizontal portions of said polysilicon film and wherein said anisotropically etching said polysilicon layer comprises forming said horizontal parts from said horizontal portions.
5. The method as in claim 1 , wherein said polysilicon segments are essentially L-shaped.
6. A method for forming a split gate flash cell comprising:
forming segments of a sacrificial film over a substrate, said segments bounded by sidewalls;
depositing a polysilicon layer covering and interposed between said segments;
depositing an oxide over said polysilicon layer;
anisotropically etching said oxide to produce spacers therefrom, said spacers disposed adjacent vertical portions of said polysilicon layer that are adjacent said sidewalls;
using said spacers as masks and anisotropically etching said polysilicon layer to form polysilicon segments therefrom, each said polysilicon segment including a vertical part and a horizontal part;
forming a second polysilicon layer over a further oxide formed over said polysilicon segments;
forming hard mask spacers along vertical sections of said second polysilicon layer thereby forming a mask of at least said hard mask spacers; and
etching portions of said second polysilicon layer not covered by said mask;
forming floating gate transistors using said polysilicon segments as said floating gates,
wherein said depositing a polysilicon layer interposed between said segments comprises depositing said polysilicon layer on a gate dielectric layer formed on said substrate between said segments.
7. The method as in claim 6 , further comprising:
forming a photoresist layer over said hard mask spacers and said second polysilicon layer; and
patterning said photoresist layer; and
wherein said mask is a composite mask including said hard mask spacers and said patterned photoresist layer.
8. The method as in claim 7 , further comprising removing said segments of said sacrificial film prior to said forming a second polysilicon layer.
9. The method as in claim 7 , wherein said floating gates comprise at least two adjacent floating gates having vertical faces facing one another and said vertical sections of said second polysilicon layer are disposed along said vertical faces and further comprising, after said etching said second polysilicon layer, using said etched second polysilicon layer as a mask and implanting to form a common drain area in said substrate between said adjacent floating gates.
10. The method as in claim 7 , wherein said depositing an oxide comprises TEOS (tetraethyl orthosilicate) and said further oxide comprises TEOS.
11. A method for forming a split gate flash cell comprising:
forming segments of a sacrificial film over a substrate, said segments bounded by sidewalls;
depositing a polysilicon layer covering and interposed between said segments;
anisotropically etching said polysilicon film to form polysilicon spacers adjacent said sidewalls;
removing said segments of said sacrificial film;
depositing an oxide over said polysilicon spacers; and
forming floating gate transistors using said polysilicon spacers as said floating gates by forming a second polysilicon layer over said oxide formed over said polysilicon spacers;
forming hard mask spacers along vertical sections of said second polysilicon layer; and
etching said second polysilicon layer using at least said hard mask spacers as a mask, thereby removing portions of said second polysilicon layer not covered by said mask.
12. The method as in claim 11 , wherein said sacrificial film comprises silicon nitride and said forming segments of a sacrificial film comprises forming said sacrificial film over said substrate and patterning said sacrificial film to form said segments therefrom.
13. The method as in claim 11 , wherein said depositing a polysilicon layer interposed between said segments comprises depositing said polysilicon layer on a gate dielectric layer formed on said substrate between said segments.
14. The method as in claim 13 , wherein said forming floating gate transistors further includes:
forming a photoresist layer over said hard mask spacers and said second polysilicon layer;
patterning said photoresist layer; and
wherein said mask is a composite mask including said hard mask spacers and said patterned photoresist layer.
15. The method as in claim 14 , wherein said floating gates comprise at least two adjacent floating gates having vertical faces facing one another and said vertical sections of said second polysilicon layer are disposed along said vertical faces and further comprising, after said etching said second polysilicon layer, using said etched second polysilicon layer as a mask and implanting to form a common drain area in said substrate between said adjacent floating gates.