Semiconductor apparatus and breakdown voltage control method of the same
A semiconductor apparatus operates based on a first voltage, a second voltage lower than the first voltage, and a third voltage in between the first and second voltages, and includes an output circuit including at least one transistor where a signal having an amplitude ranging from the second to first voltages is input to a gate, and a control circuit that generates a first control signal controlling a gate voltage of a transistor included in the output circuit, a second control signal controlling a voltage in a back-gate region of the transistor, and a third control signal controlling a voltage in a deep well region. The control circuit sets a voltage difference between the first and second control signals to be equal to or smaller than the larger one of a voltage difference between the first and third voltages and a voltage difference between the second and third voltages.
1. A semiconductor apparatus that operates based on a first power supply for supplying a first voltage, a second power supply for supplying a second voltage lower than the first voltage, and a third power supply for supplying a third voltage in between the first voltage and the second voltage, comprising:
an output circuit that includes at least one transistor where a signal having an amplitude ranging from the second voltage to the first voltage is input to a gate, and outputs a first output signal having an amplitude ranging from the second voltage to the first voltage; and
a control circuit that generates, based on an input signal, a first control signal for controlling a voltage at a gate of a transistor included in the output circuit, a second control signal for controlling a voltage in a back-gate region of the transistor, and a third control signal for controlling a voltage in a deep well region providing electrical isolation between the back-gate region and a semiconductor substrate region,
wherein the control circuit sets a voltage difference between the first control signal and the second control signal to be equal to or smaller than a larger one of a voltage difference between the first voltage and the third voltage and a voltage difference between the second voltage and the third voltage.
2. The semiconductor apparatus according to claim 1 , wherein
the control circuit generates the first control signal having an amplitude ranging from the second voltage to the first voltage,
when bringing an NMOS transistor among the transistor into conduction, the control circuit sets a voltage difference between the first control signal and the second control signal to a voltage difference between the first voltage and the third voltage and sets a voltage difference between the third control signal and the second control signal to a voltage difference between the first voltage and the third voltage,
when bringing the NMOS transistor out of conduction, the control circuit sets the first to third control signals to the second voltage,
when bringing a PMOS transistor among the transistor into conduction, the control circuit sets a voltage difference between the first control signal and the second control signal to a voltage difference between the second voltage and the third voltage and sets the third control signal and the second control signal to the third voltage, and
when bringing the PMOS transistor out of conduction, the control circuit sets the first to third control signals to the first voltage.
3. The semiconductor apparatus according to claim 2 , wherein the NMOS transistor and the PMOS transistor have the deep well region.
4. The semiconductor apparatus according to claim 1 , wherein
the control circuit generates the first control signal set to the third voltage;
when bringing an NMOS transistor among the transistor into conduction, the control circuit sets the second control signal to the second voltage and sets the third control signal to the third voltage,
when bringing the NMOS transistor out of conduction, the control circuit sets the second control signal to the third voltage and sets the third control signal to the first voltage,
when bringing a PMOS transistor among the transistor into conduction, the control circuit sets the second and third control signals to the first voltage, and
when bringing the PMOS transistor out of conduction, the control circuit sets the second and third control signals to the third voltage.
5. The semiconductor apparatus according to claim 4 , wherein the NMOS transistor and the PMOS transistor have the deep well region.
6. The semiconductor apparatus according to claim 1 , wherein
the output circuit includes:
a buffer circuit that amplifies a current of the first output signal and outputs the amplified signal as a second output signal,
the control circuit includes:
a first buffer power supply circuit that switches a high-potential-side power supply voltage of the buffer circuit; and
a second buffer power supply circuit that switches a low-potential-side power supply voltage of the buffer circuit,
when the first output signal is the first voltage, the control circuit supplies the first power supply by the first buffer power supply circuit and supplies the third power supply by the second buffer power supply circuit, and
when the first output signal is the second voltage, the control circuit supplies the third power supply by the first buffer power supply circuit and supplies the second power supply by the second buffer power supply circuit.
7. The semiconductor apparatus according to claim 1 , wherein the control circuit includes:
an input signal analyzer that analyzes the input signal and outputs a signal level designation signal for designating voltage levels of the first to third control signals to be applied to each transistor;
a first control signal generator that generates the first to third control signals having an amplitude ranging from the third voltage to the first voltage based on the signal level designation signal;
a second control signal generator that generates the first and second control signals having an amplitude ranging from the second voltage to the third voltage based on the signal level designation signal; and
a third control signal generator that generates the first control signal having an amplitude ranging from the second voltage to the first voltage based on the signal level designation signal.
8. The semiconductor apparatus according to claim 7 , wherein
the third control signal generator includes:
a first inverter composed of an NMOS transistor and a PMOS transistor connected in series between the third power supply and the first power supply;
a PMOS switch transistor where the third voltage is applied to a gate, a source is connected to an output of the first inverter, and a drain is connected to an output node;
a second inverter composed of an NMOS transistor and a PMOS transistor connected in series between the second power supply and the third power supply; and
an NMOS switch transistor where the third voltage is applied to a gate, a source is connected to an output of the second inverter, and a drain is connected to the output node,
the first inverter inverts and outputs a signal having an amplitude ranging from the third voltage to the first voltage among the signal level designation signal, and
the second inverter inverts and outputs a signal having an amplitude ranging from the second voltage to the third voltage among the signal level designation signal.
9. The semiconductor apparatus according to claim 1 , wherein
the control circuit includes:
a first power supply switch that switches between the first power supply and the third power supply and outputs either one according to the input signal; and
a second power supply switch that switches between the second power supply and the third power supply and outputs either one according to the input signal,
the output circuit includes:
a first transfer gate that has a first terminal connected to an output of the first power supply switch;
a second transfer gate that has a first terminal connected to a second terminal of the first transfer gate, and a second terminal connected to an output terminal;
a third transfer gate that has a first terminal connected to the output terminal;
a fourth transfer gate that has a first terminal connected to a second terminal of the third transfer gate, and a second terminal connected to an output of the second power supply switch;
a first switch transistor that is connected between the third power supply and a node between the first and second transfer gates; and
a second switch transistor that is connected between the third power supply and a node between the third and fourth transfer gates,
conduction states of transistors constituting the first to fourth transfer gates and the first and second switch transistors are controlled by the first to third control signals output from the control circuit,
when the first voltage is output from the output terminal, the third and fourth transfer gates and the first switch transistor become a conducting state, the first and second transfer gates and the second switch transistor become a cut-off state, the first power supply switch outputs the first power supply, and the second power supply switch outputs the third power supply, and
when the second voltage is output from the output terminal, the third and fourth transfer gates and the first switch transistor become a cut-off state, the first and second transfer gates and the second switch transistor become a conducting state, the first power supply switch outputs the third power supply, and the second power supply switch outputs the second power supply.
10. The semiconductor apparatus according to claim 9 , wherein
the first power supply is supplied to the back-gate region and the deep well region of a transistor constituting the first transfer gate, and
the second power supply is supplied to the back-gate region and the deep well region of a transistor constituting the fourth transfer gate.
11. The semiconductor apparatus according to claim 1 , wherein the first voltage and the second voltage have substantially the same voltage difference from the third voltage.
12. A breakdown voltage control method of a semiconductor apparatus including an MOS transistor where a signal having a larger amplitude voltage than a breakdown voltage is input to a gate, comprising:
when bringing the MOS transistor into conduction, controlling a back-gate voltage of the MOS transistor to set a voltage difference between a voltage input to the gate and the back-gate voltage to be equal to or smaller than the breakdown voltage; and
when bringing the MOS transistor out of conduction, controlling a back-gate voltage of the MOS transistor to set a voltage input to the gate and the back-gate voltage to substantially the same voltage.
13. The breakdown voltage control method of the semiconductor apparatus according to claim 12 , wherein
an amplitude voltage of the signal input to the gate is substantially twice the breakdown voltage, and
when bringing the MOS transistor into conduction, a back-gate voltage of the MOS transistor is controlled to set a voltage difference between a voltage input to the gate and the back-gate voltage to be ½ of the amplitude voltage.
14. The breakdown voltage control method of the semiconductor apparatus according to claim 12 , wherein
the MOS transistor includes a deep well region providing electrical isolation between a back-gate region supplied with the back-gate voltage and a semiconductor substrate region,
when the MOS transistor has N-type conductivity, a voltage difference between the back-gate voltage and a voltage of the deep well region is set to be equal to or smaller than the breakdown voltage, and
when the MOS transistor has P-type conductivity, the back-gate voltage and a voltage of the deep well region are set to substantially the same potential.
15. The breakdown voltage control method of the semiconductor apparatus according to claim 14 , wherein
an amplitude voltage of the signal input to the gate is substantially twice the breakdown voltage, and
when bringing the MOS transistor into conduction, a back-gate voltage of the MOS transistor is controlled to set a voltage difference between a voltage input to the gate and the back-gate voltage to be ½ of the amplitude voltage.