Double-gate floating-body memory device

1. A memory device comprising:

a transistor having a floating body positioned between source and drain regions, the floating body being sandwiched between first and second insulated gates each comprising a gate electrode; and

control circuitry arranged to program the state of said floating body to have an accumulation or depletion of majority carriers by applying one of first and second voltage levels between the first gate and at least one of the source and drain regions, and to retain the programmed state of said floating body by applying a third voltage level to the second gate, said voltages being switched in a time duration shorter than 100 ns.

2. The memory device of claim 1 , wherein the gate electrode of the second gate is spaced by a first distance from said floating body, and by a second distance greater than the first distance from the source and drain regions.

3. The memory device of claim 2 , wherein the first and second distances are determined by the thickness of the insulating layer of the second gate, which is thicker between each of the source and drain regions and the gate electrode of the second gate than between the floating body and the gate electrode of the second gate.

4. The memory device of claim 2 , wherein the source and drain regions are recessed with respect to the floating body on the side of the second gate.

5. The memory device of claim 2 , wherein the second gate is formed to be narrower than the spacing between the source and the drain, and wherein regions of said body between the source and drain regions are lightly doped.

6. The memory device of claim 1 , wherein said first gate is arranged to overlap the source and drain regions by a greater distance than the overlap of the source and drain regions by said second gate.

7. The memory device of claim 1 , wherein said source and drain regions are formed to be more conductive on the side of said first gate than on the side of said second gate.

8. A memory comprising an array of memory cells, each memory cell comprising the memory device of claim 1 , wherein:

the gate electrodes of the second gates of the memory devices are coupled in rows by first word lines (WL 1 ) and the drain regions are coupled in rows by second word lines (WL 2 ), the first and second word lines being coupled to row control circuitry arranged to select rows of said memory cells by applying voltages to the first and second word lines; and

the gate electrodes of the first gates of the memory devices are coupled in columns by first bit lines (BL 1 ) and the source regions are coupled in columns by second bit lines (BL 2 ), the first and second bit lines being coupled to column control circuitry for programming or reading said memory cells.

9. An electronic device comprising the memory of claim 8 and a memory interface circuit for controlling access to said memory.

10. The memory device of claim 1 , wherein the voltages are switched in a time duration shorter than 10 ns.

11. A method of manufacturing a memory device comprising:

forming, in a thin silicon film, a floating body positioned between source and drain regions;

forming first and second gates on opposite sides of the thin silicon film, each gate comprising a gate electrode and an insulating layer positioned between the floating body and the gate electrode; and

increasing the spacing between the source and drain regions and the second gate electrode by performing, after formation of the insulating layer in oxide and of the gate electrode of the first gate, an oxidization step such that the oxide thickness at ends of the insulating layer in the areas of the source and drain regions is increased;

wherein the first and second gates are formed such that the spacing between the source and drain regions and the gate electrode of the second gate is greater than the spacing between the source and drain regions and the gate electrode of the first gate.

12. A method of operating a memory device comprising a transistor having a floating body positioned between source and drain regions, the floating body being sandwiched between first and second gates each comprising a gate electrode and an insulating layer positioned between the floating body and the gate electrode, the method comprising:

applying one of first and second voltage levels between the gate electrode of the first gate and at least one of the source and drain regions to program the state of said floating body to have an accumulation or depletion of majority carriers; and

applying a third voltage level to the gate electrode of the second gate to retain the programmed state of said floating body.