IP Library Granted Patent US 8,405,808
Granted Patent B2
US 8,405,808 · App. 12/946,000 · Granted Mar 26, 2013

Active matrix substrate and display unit provided with it

Inventors: Wataru Nakamura (Mie, JP); Atsushi Ban (Nara, JP); Shoji Okazaki (Mie, JP); Hiromitsu Katsui (Mie, JP); Yoshihiro Okada (Kanagawa, JP)
Assignee: Sharp Kabushiki Kaisha
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,405,808
App. No.
12/946,000
Granted
Mar 26, 2013
Kind
B2
Abstract

An active matrix substrate includes a substrate; scanning lines formed on the substrate; an insulating film covering the scanning lines; signal lines intersecting the scanning lines via the insulating film; switching elements formed on the substrate, each operating in response to a signal which is applied to the corresponding scanning line; and pixel electrodes each capable of being electrically connected to the corresponding signal line via the switching elements. The insulating film is a multilayer insulating film including a first insulating layer and a second insulating layer. The first insulating layer is formed of an insulating material containing an organic component, and the multilayer insulating film has a low-stack region in at least a portion of a region overlapping each switching element, the first insulating layer not being formed in the low-stack region. The active matrix substrate reduces the capacitance formed at each intersection between a scanning line and a signal line, without causing an increase in the wiring resistance or a degradation of the driving ability of switching elements.

Claims (21)

1. An active matrix substrate comprising:

a substrate;

a plurality of scanning lines formed on the substrate;

an insulating film covering the plurality of scanning lines;

a plurality of signal lines intersecting the plurality of scanning lines via the insulating film;

a plurality of thin film transistors formed on the substrate, each operating in response to a signal which is applied to the corresponding scanning line; and

a plurality of pixel electrodes each capable of being electrically connected to the corresponding signal line via the plurality of thin film transistors; wherein

each of the plurality of thin film transistors is a thin film transistor having: a gate electrode electrically connected to the corresponding scanning line; a source electrode electrically connected to the corresponding signal line; and a drain electrode electrically connected to the corresponding pixel electrode;

the insulating film is a multilayer insulating film including a first insulating layer and a second insulating layer;

the first insulating layer is formed of an insulating material containing an organic component, and is formed so as to underlie the second insulating layer;

the gate electrode is formed on the first insulating layer, and is formed of a conductive layer which is different from that of the plurality of scanning lines, the gate electrode being electrically connected to the corresponding scanning line via a contact hole which is provided in the first insulating layer; and

both of the first insulating layer and the second insulating layer are provided at intersections between the signal lines and the scanning lines.

2. The active matrix substrate of claim 1 , wherein the second insulating layer is formed of an inorganic insulating material.

3. The active matrix substrate of claim 1 , wherein the second insulating layer is formed so as to cover the gate electrode, a portion of the second insulating layer functioning as a gate insulating film.

4. The active matrix substrate of claim 1 , further comprising:

a plurality of storage capacitor lines formed on the first insulating layer; and

a plurality of storage capacitor electrodes opposing the plurality of storage capacitor lines via the second insulating layer.

5. The active matrix substrate of claim 1 , having a plurality of pixel regions arrayed in a matrix, wherein the plurality of pixel electrodes are respectively provided in the plurality of pixel regions.

6. The active matrix substrate of claim 5 , having a display region defined by the plurality of pixel regions and a non-display region located around a perimeter of the display region, the non-display region having a plurality of terminals to which signals for driving the plurality of pixel regions are input, wherein,

the multilayer insulating film has a low-stack region over substantially the entire surface of the non-display region, the first insulating layer not being formed in the low-stack region.

7. The active matrix substrate of claim 5 , wherein the multilayer insulating film has an annular low-stack region near an outer periphery of each of the plurality of pixel regions, the first insulating layer not being formed in the annular low-stack region.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 8, 2016
From: SHARP KABUSHIKI KAISHA
To: MERCK PATENT GMBH
Reel/Frame 038229/0291 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 15, 2010
From: NAKAMURA, WATARU; BAN, ATSUSHI; OKAZAKI, SHOJI; KATSUI, HIROMITSU; OKADA, YOSHIHIRO
To: SHARP KABUSHIKI KAISHA
Reel/Frame 025360/0386 →
Priority Claims (2)
JP 2004-243970 · Aug 24, 2004 · national
JP 2005-235006 · Aug 12, 2005 · national
Continuity (2)
Division 11574087
Related Publication 20110057192A1 · Mar 10, 2011