IP Library › Granted Patent US 8,407,551
Granted Patent B2
US 8,407,551 · App. 12/653,657 · Granted Mar 26, 2013

Low complexity LDCP decoding

Inventors: Fredrik Brannstrom (Mountain View, CA); Andrea Goldsmith (Menlo Park, CA)
Assignee: Quantenna Communications, Inc.
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Quick Facts
Patent No.
US 8,407,551
App. No.
12/653,657
Granted
Mar 26, 2013
Kind
B2
Abstract

A technique for low-density parity-check (LDPC) coding involves utilizing a fixed point implementation in order to reduce or eliminate reliance on floating point operations. The fixed point implementation can be used to calculate check node extrinsic L-value as part of an LDPC decoder in an LDPC system. The technique can include one or more of linear approximations, offset approximations, and node-limiting approximation. A system constructed according to the technique implements one or more of linear approximations, offset approximations, and node-limiting approximation.

Claims (44)

1. A method comprising

receiving a codework;

repeating until no new values for an extrinsic L-value computation (ELC) parameter are called for in association with decoding the codeword:

selecting an ELC parameter value from a plurality of values based upon a variable;

computing extrinsic L-values for low-density parity-check (LDPC) check nodes and variable nodes using the ELC parameter for one or more iterations;

calculating a posteriori probability (APP) L-values for the codeword;

extracting information bits associated with the decoded codeword;

forwarding the information bits; and

computing the extrinsic L-values using an approach selected from the group of approaches consisting of: sum-product (SP), box-plus (BP), a posteriori probability (APP), variations of these, and combinations of these.

2. A method comprising

receiving a codeword;

repeating until no new values for an extrinsic L-value computation (ELC) parameter are called for in association with decoding the codeword:

selecting an ELC parameter value from a plurality of values based upon a variable;

computing extrinsic L-values for low-density parity-check (LDPC) check nodes and variable nodes using the ELC parameter for one or more iterations;

calculating a posteriori probability (APP) L-values for the codeword;

extracting information bus associated with the decoded codeword;

forwarding the information bits; and

computing the extrinsic L-values using an approximation selected from the group of approximations consisting of: min-sum (MS), linear (L), offset (O), non-linear (NL), variations of these, and combinations of these.

3. A system comprising:

codeword buffer;

an offset engine;

a low density parity-check (LDPC) decoding engine coupled to the codeword buffer and the offset engine;

a data buffer coupled to the LDPC decoding engine;

wherein, in operation,

the codeword buffer contains a codeword;

the offset engine provides a bias parameter, B, where 0≦B≦ln(d c −1) to the LDPC decoding engine, wherein ‘d c ' is a number of edges going into a check node, and further wherein ‘ln' is a natural log;

the LDPC decoding engine computes extrinsic L-values for low-density parity-check (LDPC) check nodes and variable nodes using the bias parameter;

the LDPC decoding engine calculates a posteriori probability (APP) L-values for the codeword and extracts information bits associated with the decoded codeword;

the data buffer has the information bits associated with the decoded codeword.

4. The system of claim 3 , wherein the bias parameter is selected from the group of parameters consisting of a bias parameter (B), an design parameter (q), or a combination of these.

5. The system of claim 3 , further comprising,:

an attenuation engine coupled to e LDPC decoding engine, wherein, in operation,

the attenuation engine provides an attenuation parameter to the LDPC decoding engine;

the LDPC decoding engine computes extrinsic L-values for LDPC check nodes and variable nodes using the attenuation parameter.

6. The system of claim 5 , wherein the attenuation parameter is selected from the group of parameters consisting of an attenuation parameter (A), a design parameter (q), or a combination of these.

7. The system of claim 3 , further comprising:

an approximation engine coupled to the LDPC decoding engine, wherein, in operation,

the approximation engine provides a node-limiting parameter (Q) to the LDPC decoding engine; the LDPC decoding engine computes extrinsic L-values for LDPC check nodes and variable nodes using the node-limiting parameter.

8. The system of claim 3 , further comprising:

a φ lookup table coupled to the LDPC decoding engine, wherein, in operation,

the approximation engine provides a φ value to the LDPC decoding engine, wherein φ(x)=ln[(exp(x)+1)/(exp(x)−1)] and the φ value is associated with a value derived from the function φ(x);

the LDPC decoding engine computes extrinsic L-values for LDPC check nodes and variable nodes using the φ value.

9. The system of claim 3 , wherein the LDPC decoding engine implements an approach selected from the group of approaches consisting of: sum-product (SP), box-plus (BP), a posteriori probability (APP), and a combination of these, and wherein the LDPC decoding engine computes the extrinsic L-value for the check node in association with the codeword in accordance with the implemented approach.

10. The system of claim 3 , wherein the LDPC decoding engine uses an approximation selected from the group of approximations consisting of min-sum (MS), linear (L), offset (O), or non-linear (NL), and wherein the LDPC decoding engine computes the extrinsic L-value fur the check node in association with the codeword in accordance with the implemented approximation.

Assignments (10)
SECURITY INTEREST Recorded Jun 22, 2026
From: MAXLINEAR, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 075800/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS, RECORDED AT REEL 051426, FRAME 0410 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: ON SEMICONDUCTOR CONNECTIVITY SOLUTIONS, INC., AS GRANTOR
Reel/Frame 064067/0340 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2023
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: MAXLINEAR, INC.
Reel/Frame 063572/0701 →
RELEASE OF SECURITY INTEREST Recorded May 2, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: ON SEMICONDUCTOR CONNECTIVITY SOLUTIONS, INC.
Reel/Frame 063516/0736 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 6, 2023
From: ON SEMICONDUCTOR CONNECTIVITY SOLUTIONS, INC.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 063280/0591 →
MERGER AND CHANGE OF NAME Recorded Apr 6, 2023
From: RAPTOR OPERATIONS SUB, INC.; QUANTENNA COMMUNICATIONS, INC.
To: ON SEMICONDUCTOR CONNECTIVITY SOLUTIONS, INC.
Reel/Frame 063271/0657 →
PATENT SECURITY AGREEMENT Recorded Dec 26, 2019
From: ON SEMICONDUCTOR CONNECTIVITY SOLUTIONS, INC.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 051426/0410 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2019
From: SILICON VALLEY BANK
To: QUANTENNA COMMUNICATIONS, INC.
Reel/Frame 049332/0372 →
SECURITY AGREEMENT Recorded May 19, 2016
From: QUANTENNA COMMUNICATIONS, INC.
To: SILICON VALLEY BANK
Reel/Frame 038754/0371 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2010
From: BRANNSTROM, FREDRIK; GOLDSMITH, ANDREA
To: QUANTENNA COMMUNICATIONS, INC.
Reel/Frame 024051/0907 →
Continuity (2)
Provisional Application 61122648 · Dec 15, 2008
Related Publication 20100162075A1 · Jun 24, 2010