IP Library Granted Patent US 8,413,009
Granted Patent B2
US 8,413,009 · App. 13/087,290 · Granted Apr 2, 2013

ECC with out of order completion

Inventors: Kwok W. Yeung (Milpitas, CA); Kin Ming Chan (Milpitas, CA); Meng-Kun Lee (Cupertino, CA)
Assignee: SK hynix memory solutions inc.
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Quick Facts
Patent No.
US 8,413,009
App. No.
13/087,290
Granted
Apr 2, 2013
Kind
B2
Abstract

Processing a sequence of data frames in an error correction code (ECC) decoder is disclosed. Processing includes receiving a first data frame in the sequence of data frames, storing the first data frame, initiating processing of the first data frame through the ECC decoder, receiving a second data frame from the input sequence of data frames, storing the second data frame, and initiating processing of the second data frame through the ECC decoder before the first data frame is finished being processed through the ECC decoder.

Claims (34)

1. A method of processing a sequence of data frames in an error correction code (ECC) decoder, including:

receiving a first data frame in the sequence of data frames;

initiating processing of the first data frame through the ECC decoder;

receiving a second data frame from the input sequence of data frames; and

initiating processing of the second data frame through the ECC decoder before the first data frame is finished being processed through the ECC decoder.

2. A method as recited in claim 1 , wherein the ECC decoder includes two or more stages, and wherein processing of the second data frame is initiated after the first data frame is finished processing through a first stage of the ECC decoder.

3. A method as recited in claim 1 , wherein the ECC decoder includes one or more iterative stages.

4. A method as recited in claim 1 , wherein the ECC decoder processes an error indication or error correction information corresponding to the second data frame before processing an error indication or error correction information corresponding to the first data frame.

5. A method as recited in claim 1 , wherein the ECC decoder processes an intermediate error indication or intermediate error correction information corresponding to the second data frame before processing an intermediate error indication or intermediate error correction information corresponding to the first data frame.

6. A method as recited in claim 1 , wherein the ECC decoder finishes processing a sector corresponding to the second data frame before finishing processing a sector corresponding to the first data frame.

7. A method as recited in claim 1 , wherein the ECC decoder outputs a corrected second data frame corresponding to the second data frame before outputting a corrected first data frame corresponding to the first data frame.

8. A method as recited in claim 4 , 5 , 6 , or 7 , further including reordering the corrected first data frame before the corrected second data frame.

9. A method as recited in claim 1 , wherein the ECC decoder outputs a corrected second data frame corresponding to the second data frame before outputting a corrected first data frame corresponding to the first data frame, and further including reordering the corrected first data frame before the corrected second data frame.

10. A method as recited in claim 1 , wherein the ECC decoder is associated with a low density parity check (LDPC) code.

11. A method as recited in claim 1 , wherein the ECC decoder is associated with a Reed-Solomon code.

12. A method as recited in claim 1 , wherein the ECC decoder includes a soft output Viterbi algorithm (SOVA) processing stage.

13. A method as recited in claim 1 , wherein the ECC decoder uses reliability information.

14. A method as recited in claim 1 , wherein the data frames are associated with disk sectors.

15. A method as recited in claim 1 , wherein the data frames are associated with a communications system.

16. A system for processing a sequence of data frames in an error correction code (ECC) decoder, including:

a decoder configured to:

receive a first data frame in the sequence of data frames;

initiate processing of the first data frame through the ECC decoder;

receive a second data frame from the input sequence of data frames; and

initiate processing of the second data frame through the ECC decoder before the first data frame is finished being processed through the ECC decoder; and

an input interface coupled with the decoder.

17. A system as recited in claim 16 , wherein the ECC decoder includes two or more stages, and wherein processing of the second data frame is initiated after the first data frame is finished processing through a first stage of the ECC decoder.

18. A system as recited in claim 16 , wherein the ECC decoder includes one or more iterative stages.

19. A system as recited in claim 16 , wherein the ECC decoder outputs a corrected second data frame corresponding to the second data frame before outputting a corrected first data frame corresponding to the first data frame.

20. A computer program product for processing a sequence of data frames in an error correction code (ECC) decoder, the computer program product being embodied in a non-transitory computer readable medium and comprising computer instructions for:

receiving a first data frame in the sequence of data frames;

initiating processing of the first data frame through the ECC decoder;

receiving a second data frame from the input sequence of data frames; and

initiating processing of the second data frame through the ECC decoder before the first data frame is finished being processed through the ECC decoder.

Assignments (2)
CHANGE OF NAME Recorded Feb 22, 2013
From: LINK_A_MEDIA DEVICES CORPORATION
To: SK HYNIX MEMORY SOLUTIONS INC.
Reel/Frame 029860/0408 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 14, 2011
From: YEUNG, KWOK W.; CHAN, KIN MING; LEE, MENG-KUN
To: LINK_A_MEDIA DEVICES CORPORATION
Reel/Frame 026443/0282 →
Continuity (3)
Continuation 11787140 · Apr 13, 2007
Provisional Application 60920882 · Mar 30, 2007
Related Publication 20110239085A1 · Sep 29, 2011