Methods of manufacturing semiconductor devices
A semiconductor device may include lower electrodes having different heights depending on positions on a substrate. Supporting layer pattern making a contact with the lower electrodes having a relatively large height is provided. The supporting layer pattern is provided between the lower electrodes for supporting the lower electrodes. A dielectric layer is provided on the lower electrodes and the supporting layer pattern. An upper electrode is formed on the dielectric layer and has a planar upper surface. An inter-metal dielectric layer is provided on the upper electrode. A metal contact penetrating through the inter-metal dielectric layer and making a contact with the upper electrode is formed. A bottom portion of the metal contact faces a portion under where the lower electrode having a relatively small height is formed. The device has a higher reliability.
1. A method of manufacturing a semiconductor device, the method comprising:
forming preliminary lower electrodes and a supporting layer supporting upper sidewalls of the preliminary lower electrodes;
partially etching the supporting layer and an upper portion of the preliminary lower electrodes to form a supporting layer pattern and lower electrodes, each of the lower electrodes having a taller side with a height that is greater than an opposing shorter side, the supporting layer pattern contacting the taller sides of the lower electrodes;
forming a dielectric layer on the lower electrodes and the supporting layer pattern;
forming an upper electrode on the dielectric layer;
forming an inter-metal dielectric layer on the upper electrode; and
forming a metal contact penetrating the inter-metal dielectric layer and contacting the upper electrode, a bottom portion of the metal contact being aligned above the shorter sides of the lower electrodes.
2. The method of claim 1 , further comprising:
forming a conductive line on the substrate, the conductive line contacting a bottom portion of the lower electrodes.
3. The method of claim 1 , wherein the partially etching includes removing portions of the supporting layer and the preliminary lower electrodes that would be aligned below the bottom portion of the metal contact.
4. The method of claim 1 , wherein the forming a metal contact includes aligning the metal contact with an inner portion of a gap between adjacent supporting layer patterns.
5. The method of claim 1 , wherein the forming preliminary lower electrodes and a supporting layer comprises:
forming a first mold layer, the supporting layer, and a second mold layer on the substrate;
partially etching the second mold layer, the supporting layer, and the first mold layer to form opening portions; and
forming the lower electrodes in the opening portions.
6. The method of claim 5 , further comprising:
forming a capping layer in the opening portions including the lower electrodes and on the second mold layer.
7. The method of claim 6 , further comprising:
removing the capping layer, the first mold layer, and the second mold layer after forming the supporting layer pattern.
8. The method of claim 1 , wherein the partially etching includes forming the supporting layer pattern to have a pattern shape or a line shape, the pattern shape including a hole.
9. The method of claim 1 , wherein the partially etching, the forming a dielectric layer, and the forming an upper electrode include forming the lower electrodes, the dielectric layer, the upper electrode, and the supporting layer pattern in a peripheral region of the substrate, the lower electrodes, the dielectric layer, and the upper electrode constituting at least one capacitor.