Semiconductor device including diode

1. A semiconductor device, comprising:

a cathode; and

an anode including a first p-type semiconductor anode region and a second p-type semiconductor anode region, the first p-type semiconductor anode region being electrically connected to an anode contact area, the second p-type semiconductor anode region being electrically coupled to the anode contact area via a switch configured to provide an electrical connection or an electrical disconnection between the second p-type semiconductor anode region and the anode contact area.

2. The semiconductor device of claim 1 , wherein a dose of n-type doping in a first portion of the cathode opposite the first p-type semiconductor anode region is smaller than the dose of n-type doping in a second portion of the cathode opposite the second p-type semiconductor anode region.

3. The semiconductor device of claim 2 , wherein a ratio of the dose of the n-type doping in the second portion of the cathode to the dose of the n-type doping in the first portion of the cathode is between 5 to 10 4 .

4. The semiconductor device of claim 1 , wherein a dose of p-type doping in the first p-type semiconductor anode region is smaller than the dose of p-type doping in the second p-type semiconductor anode region.

5. The semiconductor device of claim 4 , wherein a ratio of the dose of the p-type doping in the second p-type semiconductor anode region to the dose of the p-type doping in the first p-type semiconductor anode region is between 5 to 10 4 .

6. The semiconductor device of claim 1 , wherein a bottom side of the second p-type semiconductor anode is located deeper within a semiconductor substrate than a bottom side of the first p-type semiconductor region.

7. The semiconductor device of claim 1 , further comprising:

an n-type drift zone arranged between the first p-type semiconductor region and the second p-type semiconductor region and between the cathode and the anode.

8. The semiconductor device of claim 1 , wherein the first p-type semiconductor anode region is part of a merged pin Schottky diode.

9. The semiconductor device of claim 1 , wherein the switch includes a field effect transistor.

10. The semiconductor device of claim 9 , wherein the second p-type semiconductor region is one of a source and a drain of the field effect transistor.

11. The semiconductor device of claim 10 , wherein the switch is one of a planar field effect transistor including a lateral channel or a trench field effect transistor including a vertical channel.

12. The semiconductor device of claim 10 , wherein the switch includes a first auxiliary n-type region and a second auxiliary p-type region, the second auxiliary p-type region being the other one of the source and the drain of the field effect transistor.

13. The semiconductor switch of claim 12 , wherein the first auxiliary n-type region and the second auxiliary p-type region are electrically connected to the anode contact area.

14. The semiconductor device of claim 13 , wherein:

the switch is a planar field effect transistor including a lateral channel;

the first auxiliary n-type region is arranged in the second p-type semiconductor anode region;

the second auxiliary p-type region is arranged in the first auxiliary n-type region;

the second p-type semiconductor anode region, the first auxiliary n-type region and the second auxiliary p-type region each adjoin a surface of a semiconductor substrate; and

a gate is arranged above the first auxiliary n-type region, the gate being configured to control a conductivity of a channel located in the first auxiliary n-type region at the surface between the second auxiliary p-type region and the second p-type semiconductor anode region.

15. The semiconductor device of claim 14 , wherein an extension of the gate along a channel direction parallel to the surface between the source and the drain of the planar field effect transistor ends above the second p-type semiconductor anode region.

16. The semiconductor device of claim 14 , wherein an extension of the gate along a channel direction parallel to the surface between the source and the drain of the planar field effect transistor ends above an n-type drift zone.

17. The semiconductor device of claim 1 , wherein a blocking capability between the anode and the cathode is between 0.6 kV and 10 kV.

18. The semiconductor device of claim 13 , wherein:

the switch is a trench field effect transistor including a vertical channel;

the first auxiliary n-type region is arranged in the second p-type semiconductor anode region;

the second auxiliary p-type region is arranged in the first auxiliary n-type region;

the first auxiliary n-type region and the second auxiliary p-type region adjoin a surface of a semiconductor substrate; and

a gate electrode is arranged within a trench, the gate electrode being configured to control the conductivity of a channel located in the first auxiliary n-type region at a sidewall of the trench between the second auxiliary p-type region and the second p-type semiconductor anode region.

19. The semiconductor device of claim 18 , wherein a bottom side of the gate electrode ends deeper within the semiconductor substrate than a bottom side of the second p-type anode region.

20. The semiconductor device of claim 18 , wherein a bottom side of the gate electrode within the semiconductor substrate ends at a same level with or above a bottom side of the second p-type anode region.

21. The semiconductor device of claim 1 , wherein the first p-type semiconductor anode region adjoins a trench isolation.

22. The semiconductor device of claim 1 , wherein minority carrier lifetime is higher in the second p-type semiconductor anode region than in the first p-type semiconductor anode region.

23. The semiconductor device of claim 22 , wherein a ratio of the minority carrier lifetime in the second p-type semiconductor anode region to the minority carrier lifetime in first p-type semiconductor anode region is between 5 to 10 4 .

24. The semiconductor device of claim 1 , wherein an efficiency of the second p-type semiconductor anode region is higher than an efficiency of the first p-type semiconductor anode region.

25. The semiconductor device of claim 24 , wherein a ratio of the efficiency of second p-type semiconductor anode region to the efficiency of the first p-type semiconductor anode region is between 5 to 10 4 .