Shift register

1. A shift register comprising a plurality of stages for sequentially outputting scan pulses, wherein an nth one of the stages (where n is a natural number) comprises:

a node controller for controlling voltages at nodes; and

an output unit for outputting any one of a corresponding one of the scan pulses and a first discharging voltage in response to the voltages at the nodes,

wherein the nodes comprise a set node, a first reset node and a second reset node,

wherein the node controller of the nth stage comprises:

a first switching device controlled by a voltage supplied to the first reset node for supplying a second discharging voltage to the set node;

a second switching device controlled by a voltage supplied to the second reset node for supplying the second discharging voltage to the set node;

a first inverter circuit controlled by a voltage supplied to the set node for supplying any one of a first charging voltage and a third discharging voltage to the first reset node; and

a second inverter circuit controlled by the voltage supplied to the set node for supplying any one of a second charging voltage and a fourth discharging voltage to the second reset node, and

wherein the third discharging voltage and the fourth discharging voltage are lower than the second discharging voltage.

2. The shift register according to claim 1 , wherein:

the first inverter circuit supplies the third discharging voltage to the first reset node when a voltage corresponding to a high logic value is supplied to the set node, and supplies the first charging voltage to the first reset node when a voltage corresponding to a low logic value is supplied to the set node; and

the second inverter circuit supplies the fourth discharging voltage to the second reset node when the voltage corresponding to the high logic value is supplied to the set node, and supplies the second charging voltage to the second reset node when the voltage corresponding to the low logic value is supplied to the set node,

wherein each of the first charging voltage and second charging voltage alternately has a high voltage and a low voltage at intervals of m frame periods (where m is a natural number), and

wherein the first charging voltage and the second charging voltage have different voltages in the same frame period.

3. The shift register according to claim 2 , wherein:

the first inverter circuit comprises:

a first inverting switching device controlled according to the first charging voltage and connected between a first charging voltage line transferring the first charging voltage and the first reset node; and

a second inverting switching device controlled according to a voltage at the set node and connected between the first reset node and a third discharging voltage line transferring the third discharging voltage; and

the second inverter circuit comprises:

a third inverting switching device controlled according to the second charging voltage and connected between a second charging voltage line transferring the second charging voltage and the second reset node; and

a fourth inverting switching device controlled according to the voltage at the set node and connected between the second reset node and a fourth discharging voltage line transferring the fourth discharging voltage.

4. The shift register according to claim 2 , wherein:

the first inverter circuit comprises:

a first inverting switching device controlled according to an external first control signal and connected between a first charging voltage line transferring the first charging voltage and the first reset node; and

a second inverting switching device controlled according to a voltage at the set node and connected between the first reset node and a third discharging voltage line transferring the third discharging voltage; and

the second inverter circuit comprises:

a third inverting switching device controlled according to an external second control signal and connected between a second charging voltage line transferring the second charging voltage and the second reset node; and

a fourth inverting switching device controlled according to the voltage at the set node and connected between the second reset node and a fourth discharging voltage line transferring the fourth discharging voltage.

5. The shift register according to claim 2 , wherein:

the first inverter circuit comprises:

a first inverting switching device controlled according to the first charging voltage and connected between a first charging voltage line transferring the first charging voltage and a first common node;

a second inverting switching device controlled according to a voltage at the set node and connected between the first common node and a fifth discharging voltage line transferring a fifth discharging voltage;

a third inverting switching device controlled according to a voltage at the first common node and connected between the first charging voltage line and the first reset node; and

a fourth inverting switching device controlled according to the voltage at the set node and connected between the first reset node and a third discharging voltage line transferring the third discharging voltage; and

the second inverter circuit comprises:

a fifth inverting switching device controlled according to the second charging voltage and connected between a second charging voltage line transferring the second charging voltage and a second common node;

a sixth inverting switching device controlled according to the voltage at the set node and connected between the second common node and a sixth discharging voltage line transferring a sixth discharging voltage;

a seventh inverting switching device controlled according to a voltage at the second common node and connected between the second charging voltage line and the second reset node; and

an eighth inverting switching device controlled according to the voltage at the set node and connected between the second reset node and a fourth discharging voltage line transferring the fourth discharging voltage.

6. The shift register according to claim 1 , wherein the first discharging voltage is the same as any one of the second discharging voltage and third discharging voltage.

7. The shift register according to claim 1 , wherein the first discharging voltage is lower than the second discharging voltage.

8. The shift register according to claim 1 , wherein the third discharging voltage is the same as the fourth discharging voltage.

9. The shift register according to claim 1 , wherein the third discharging voltage and the fourth discharging voltage are lower than the first discharging voltage.

10. The shift register according to claim 1 , wherein the node controller of the nth stage further comprises:

a third switching device controlled by a scan pulse from an (n−p)th one of the stages (where p is a natural number less than n) and connected between a charging voltage line transferring a charging voltage and the set node; and

a fourth switching device controlled by a scan pulse from an (n+q)th one of the stages (where q is a natural number) and connected between the set node and a second discharging voltage line transferring the second discharging voltage.

11. The shift register according to claim 10 , wherein the node controller of the nth stage further comprises:

a fifth switching device controlled by the scan pulse from the (n−p)th stage and connected between the first reset node and a third discharging voltage line transferring the third discharging voltage; and

a sixth switching device controlled by the scan pulse from the (n−p)th stage and connected between the second reset node and the third discharging voltage line.

12. The shift register according to claim 1 , wherein the output unit of the nth stage comprises:

a pull-up switching device controlled by a voltage at the set node and connected between a clock transfer line transferring any one of a plurality of clock pulses having phase differences thereamong and an output terminal of the nth stage;

a first pull-down switching device controlled by a voltage at the first reset node and connected between the output terminal and a first discharging voltage line transferring the first discharging voltage; and

a second pull-down switching device controlled by a voltage at the second reset node and connected between the output terminal and the first discharging voltage line transferring the first discharging voltage.

13. The shift register according to claim 4 , wherein each of the first and second control signals is any one of a plurality of clock pulses having phase differences thereamong,

wherein each of the first and second control signals supplied respectively to the first and third inverting switching devices in the nth stage is one of the clock pulses corresponding to the scan pulse output from the nth stage.

14. The shift register according to claim 5 , wherein the third to sixth discharging voltages are all the same.