IP Library › Granted Patent US 8,436,431
Granted Patent B2
US 8,436,431 · App. 13/014,060 · Granted May 7, 2013

Semiconductor device including gate and three conductor electrodes

Inventor: Yasuhiko Takemura (Isehara, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
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Quick Facts
Patent No.
US 8,436,431
App. No.
13/014,060
Granted
May 7, 2013
Kind
B2
Abstract

An object is to provide a field effect transistor (FET) having a conductor-semiconductor junction, which has excellent characteristics, which can be manufactured through an easy process, or which enables high integration. Owing to the junction between a semiconductor layer and a conductor having a work function lower than the electron affinity of the semiconductor layer, a region into which carriers are injected from the conductor is formed in the semiconductor layer. Such a region is used as an offset region of the FET or a resistor of a semiconductor circuit such as an inverter. Further, in the case of setting up such an offset region and a resistor in one semiconductor layer, an integrated semiconductor device can be manufactured.

Claims (14)

1. A semiconductor device comprising:

a semiconductor layer;

a first conductor electrode, a second conductor electrode, and a third conductor electrode which are provided in contact with one surface of the semiconductor layer; and

a gate provided on the other surface side of the semiconductor layer,

wherein the gate overlaps with at least part of a region between the first conductor electrode and the second conductor electrode, and

wherein the gate does not overlap with a region between the second conductor electrode and the third conductor electrode.

2. The semiconductor device according to claim 1 , wherein a portion of the first conductor electrode and a portion of the second conductor electrode which are in contact with the semiconductor layer have a work function lower than a sum of an electron affinity of the semiconductor layer and 0.3 electron volts.

3. The semiconductor device according to claim 1 , wherein an ohmic junction is formed between the semiconductor layer and the first conductor electrode and between the semiconductor layer and the second conductor electrode.

4. The semiconductor device according to claim 1 , further comprising a gate insulating film between the semiconductor layer and the gate.

5. The semiconductor device according to claim 1 , wherein a work function of a portion of the gate which is the closest to the semiconductor layer is higher than a sum of an electron affinity of the semiconductor layer and 0.6 electron volts.

6. The semiconductor device according to claim 1 , wherein a width of a first portion of the semiconductor layer between the first conductor electrode and the second conductor electrode is wider than that of a second portion of the semiconductor layer between the second conductor electrode and the third conductor electrode.

7. The semiconductor device according to claim 1 , wherein the semiconductor layer comprises an i-type semiconductor.

8. The semiconductor device according to claim 1 , wherein the gate comprises a material selected from the group consisting of platinum, gold, tungsten, and indium nitride.

9. The semiconductor device according to claim 1 , wherein the semiconductor device is an inverter.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 26, 2011
From: TAKEMURA, YASUHIKO
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 025700/0072 →
Priority Claims (1)
JP 2010-024580 · Feb 5, 2010 · national
Continuity (1)
Related Publication 20110193182A1 · Aug 11, 2011