IP Library Granted Patent US 8,446,020
Granted Patent B2
US 8,446,020 · App. 12/902,527 · Granted May 21, 2013

Multi-chip module

Inventors: Masateru Koide (Kawasaki, JP); Daisuke Mizutani (Kawasaki, JP); Aiichiro Inoue (Kawasaki, JP); Hideo Yamashita (Kawasaki, JP); Iwao Yamazaki (Kawasaki, JP); Masayuki Kato (Kawasaki, JP); Seiji Ueno (Yokohama, JP); Kazuyuki Imamura (Yokohama, JP)
Assignees: Fujitsu Limited; Fujitsu Semiconductor Limited
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Quick Facts
Patent No.
US 8,446,020
App. No.
12/902,527
Granted
May 21, 2013
Kind
B2
Abstract

A multi-chip module includes: a board; a wiring board disposed on the board and including a wiring pattern; and a plurality of chips disposed on the wiring board. Each of the plurality of chips is connected with at least one of the other chips, and the plurality of chips and the board are electrically connected with each other via a portion other than the wiring pattern of the wiring board.

Claims (14)

1. A multi-chip module comprising:

a board;

a wiring board disposed on the board and including a wiring pattern; and

a plurality of chips disposed on the wiring board,

wherein each of the plurality of chips is connected with at least one of the other chips, and the plurality of chips and the board are electrically connected with each other via a portion other than the wiring pattern of the wiring board,

wherein each of the plurality of chips is electrically connected with at least one of the other chips via the wiring pattern, and

wherein the wiring board is a silicon interposer, the silicon interposer including another board and an insulating layer disposed on the another board, the wiring pattern being formed in the insulating layer.

2. The multi-chip module of claim 1 , wherein the wiring pattern is formed by semiconductor manufacture equipment.

3. The multi-chip module of claim 1 , wherein a length of the wiring between the plurality of chips is equal to or less than 1.5 mm.

4. The multi-chip module of claim 1 , wherein the plurality of the chips include four chips arranged in a matrix manner, and the each of chips is connected with at least one of the other chips via the wiring pattern at an area where all of the four chips are adjacent to each other.

5. The multi-chip module of claim 1 , wherein the plurality of chips and the board are electrically connected with each other via via holes penetrating through the wiring board.

6. The multi-chip module of claim 5 , wherein a clearance between the wiring patterns is smaller than a clearance between the via holes.

7. The multi-chip module of claim 1 , wherein the plurality of chips are LSI chips.

8. The multi-chip module of claim 1 , wherein the wiring pattern is formed in multiple layers of the insulating layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2015
From: FUJITSU SEMICONDUCTOR LIMITED
To: SOCIONEXT INC.
Reel/Frame 035498/0324 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 12, 2010
From: KOIDE, MASATERU; MIZUTANI, DAISUKE; INOUE, AIICHIRO; YAMASHITA, HIDEO; YAMAZAKI, IWAO; KATO, MASAYUKI; UENO, SEIJI; IMAMURA, KAZUYUKI
To: FUJITSU LIMITED; FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 025125/0454 →
Priority Claims (1)
JP 2009-239489 · Oct 16, 2009 · national
Continuity (1)
Related Publication 20110089579A1 · Apr 21, 2011