Serial bus device and clock difference compensation method thereof
A serial bus device for transmitting a packet to a link partner is provided. The serial bus device includes a processing unit and a clock difference compensation unit coupled to the processing unit. The processing unit generates the packet. The clock difference compensation unit determines whether to transmit at least one skip ordered set to the link partner prior to the packet according to a type of the packet, so as to compensate for a clock difference for the link partner.
1. A serial bus device for transmitting a packet to a link partner, comprising:
a processing unit, generating the packet; and
a clock difference compensation unit coupled to the processing unit, determining whether to transmit at least one skip ordered set to the link partner prior to the packet according to a type of the packet, so as to compensate for a clock difference for the link partner,
wherein the clock difference compensation unit comprises:
a skip symbol generator, generating the skip ordered set which comprises two skip symbols; and
an arbitrator coupled between the processing unit and the skip symbol generator, determining whether to transmit the skip ordered set to the link partner prior to the packet according to the type of the packet.
2. The serial bus device as claimed in claim 1 , wherein the arbitrator identifies the type of the packet according to a type field within a header of the packet.
3. The serial bus device as claimed in claim 1 , wherein the arbitrator determines whether to transmit the skip ordered set to the link partner prior to the packet according to a data length of the packet when the packet is a data packet.
4. The serial bus device as claimed in claim 1 , wherein the arbitrator directly transmits the packet to the link partner when the packet is not a data packet.
5. The serial bus device as claimed in claim 3 , wherein the arbitrator transmits the skip ordered set to the link partner prior to the packet when the packet is the data packet and the data length of the packet is larger than or equal to a specific value.
6. The serial bus device as claimed in claim 5 , wherein the arbitrator directly transmits the packet to the link partner when the packet is the data packet and the data length of the packet is smaller than the specific value.
7. The serial bus device as claimed in claim 3 , wherein the arbitrator obtains the data length of the packet according to a data length field within a header of the packet.
8. The serial bus device as claimed in claim 3 , wherein the arbitrator controls the skip symbol generator to generate the skip ordered set when the packet is the data packet and the data length of the packet is larger than or equal to a specific value, and a quantity of the skip ordered set generated by the skip symbol generator corresponds to the data length of the packet.
9. A clock difference compensation method for a serial bus device, comprising:
determining whether a packet to be transmitted to a link partner is a data packet;
transmitting at least one skip ordered set to the link partner prior to the packet when the packet is the data packet and a data length of the packet is larger than or equal to a specific value, so as to compensate for a clock difference between the serial bus device and the link partner; and
directly transmitting the packet to the link partner when the packet is not the data packet.
10. The clock difference compensation method as claimed in claim 9 , further comprising:
directly transmitting the packet to the link partner when the packet is the data packet and the data length of the packet is smaller than the specific value.
11. The clock difference compensation method as claimed in claim 9 , further comprising:
determining a quantity of the skip ordered set to be transmitted to the link partner according to the data length of the packet.
12. The clock difference compensation method as claimed in claim 11 , wherein the quantity of the skip ordered set corresponds to the data length of the packet.
13. The clock difference compensation method as claimed in claim 11 , wherein the quantity of the skip ordered set is fixed.
14. The clock difference compensation method as claimed in claim 9 , wherein the step of determining further comprises:
determining whether the packet is the data packet according to a type field within a header of the packet; and
obtaining the data length of the packet according to a data length field within the header of the packet when the packet is the data packet.
15. The clock difference compensation method as claimed in claim 9 , wherein the skip ordered set comprises two skip symbols.