MOS varactor structure and methods

1. An apparatus, comprising:

a semiconductor substrate;

a rectangular active area defined in a portion of the semiconductor substrate;

a doped well region in the active area extending into the semiconductor substrate;

at least two gate structures comprising rectangular shapes disposed in parallel and spaced apart over the doped well region, the gate structures comprising gate conductors lying over gate dielectric material;

source and drain regions corresponding to each of the at least two gate structures, forming rectangular shapes parallel to the gate structures and disposed in the well region formed on opposing sides of the gate structures;

at least two gate strap conductors disposed over the active area comprising the gate conductor material and arranged in parallel to one another and perpendicular to the at least two gate structures, the at least two gate strap conductors electrically coupling the at least two gate structure conductors to one another;

a first interlevel dielectric layer overlying the gate conductors and the gate strap conductors;

a gate connector formed in a first metal layer overlying the first interlevel dielectric layer and overlying the at least two gate structures and electrically coupling the at least two gate structures via contact structures formed in the interlevel dielectric layer and extending to the at least two gate structures;

source and drain connectors formed in a second metal layer and overlying the source and drain regions in the well region and electrically coupled to the source and drain regions; and

a second level of interlevel dielectric material electrically separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer.

2. The apparatus of claim 1 , wherein no portion of the gate connector is formed in the second metal layer.

3. The apparatus of claim 1 , wherein the first metal layer gate connector is disposed overlying a central portion of the active area.

4. The apparatus of claim 1 , wherein the gate structures comprise polysilicon.

5. The apparatus of claim 4 , wherein the gate structures comprise doped polysilicon.

6. The apparatus of claim 1 wherein the gate connector in the first metal layer is further coupled to the gate strap conductors via contacts formed in the first interlevel dielectric layer.

7. The apparatus of claim 6 , wherein the gate connector is T-shaped when viewed from a plan view perspective.

8. The apparatus of claim 1 , wherein the source and drain connectors are coupled to the source and drain regions by vertical connectors, comprising:

a via formed in the second interlevel dielectric layer and electrically coupling the second metal layer to a first metal layer portion; and

a contact formed in a via in the first interlevel dielectric layer coupling the first metal layer portion to source and drain regions in the well.

9. The apparatus of claim 8 wherein the vertical connectors are formed in corner portions of the active area.

10. An apparatus, comprising:

circuitry formed on a semiconductor substrate having a frequency dependent function, the circuitry including inductors and at least one tunable varactor cell, the at least one varactor cell further comprising:

an active area defined in a portion of the semiconductor substrate;

a doped well region in the active area extending into the semiconductor substrate;

at least two gate structures disposed in parallel over the doped well region and arranged in a first direction, the gate structures comprising conductors lying over gate dielectric material;

source and drain regions disposed in the well region formed on opposing sides of the gate structures and aligned in parallel to the gate structures;

at least two gate strap conductors disposed over the active area comprising the gate conductor material and arranged in parallel to one another and in a second direction perpendicular to the first direction, the at least two gate strap conductors electrically coupling the at least two gate structure conductors to one another;

a first interlevel dielectric layer overlying the at least two gate structure conductors and the at least two gate strap conductors;

a gate connector formed in a first metal layer overlying the first level dielectric layer over the at least two gate structures and electrically coupling the at least two gate structures via contacts formed in the first level dielectric layer;

source and drain connectors formed in a second metal layer and overlying the source and drain regions in the well region and electrically coupled to the source and drain regions; and

a second interlevel dielectric layer electrically separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer.

11. The apparatus of claim 10 wherein the at least one varactor cell further comprises an array of identical varactor cells coupled together.

12. The apparatus of claim 10 wherein the second metal layer overlying the array of varactor cells is free from any electrical connection to the gate connector.

13. The apparatus of claim 10 , wherein the circuitry provided on the substrate having a frequency dependent function further comprises a voltage controlled oscillator, the circuitry further comprising a variable capacitor bank comprising the at least one tunable varactor and additional variable capacitors, and the gain K of the voltage controlled oscillator is determined by adjusting the capacitance provided by the additional variable capacitors, and adjusting the capacitance provided by tuning the at least one tunable varactor.