Automated conversion of synchronous to asynchronous circuit design representations

1. A method, comprising:

generating a synchronous netlist from a synchronous circuit design, the synchronous netlist including combinational logic gates and state-holding elements;

converting the synchronous netlist to an asynchronous circuit design, the converting including grouping the combinational logic gates by operations into functions; and

generating annotations by an annotation generator to map performance chartacteristics from the asychronous circuit design into the synchronous circuit design to validate timing characteristics of the asynchronous circuit design.

2. The method of claim 1 , wherein the generating comprises:

generating the synchronous netlist to include modules from an electronic design interchange format (EDIF).

3. The method of claim 1 , further comprising:

representing the asynchronous circuit design by a least one of a dataflow graph, a detailed description of the implementation of the dataflow graph, or a high-level language.

4. The method of claim 3 , further comprising:

representing data as tokens when the asynchronous circuit design is represented by a dataflow graph.

5. The method of claim 3 , further comprising:

implementing the dataflow graph using synchronous logic.

6. The method of claim 3 , wherein the dataflow graph comprises:

at least one of a function block, a source block, a sink block, a copy block, a merge block, or an initial block.

7. The method of claim 1 , wherein the converting comprises:

validating timing characteristics of the asynchronous design using the annotations.

8. The method of claim 1 wherein the generating comprises:

generating the synchronous netlist to include at least one of a synchronous clock, a synchronous clock frequency, or a multi-cycle path.

9. The method of claim 1 , wherein the synchronous circuit design comprises a single clock domain and the converting includes:

ignoring clock and clock enable inputs; and

specifying a logic computation for a functional group of the combinational logic gates.

10. The method of claim 1 , further comprising:

assuming an ideal logic delay and ideal state-holding elements.

11. The method of claim 1 , wherein the synchronous design comprises:

multiple clock domains, and wherein the converting includes determining a repeating period that corresponds to a least common multiple of selected clock cycle times associated with the synchronous circuit design.

12. The method of claim 1 , further comprising:

separating selected ones of the state-holding elements into clock domains.

13. The method of claim 1 , wherein the state-holding elements comprise:

gated clocks, and wherein the converting includes at least one of removing gates by substituting a multiplexer transformation or using gating information to transform an output of at least some of the state-holding elements into a conditional signal.

14. The method of claim 1 , further comprising:

selecting an asynchronous combinational logic function in the asynchronous design;

identifying a condition token and a data token for the asynchronous combinational logic function;

buffering the condition token and data token; and

generating an unconditional data token matching an output value of the asynchronous combinational logic function for at least some of the clock signals of the selected asynchronous combinational logic function to convert the selected asynchronous combinational logic function into a synchronous combinational logic function.

15. The method of claim 1 , wherein the converting comprises:

leaving synchronous input signals and synchronous output signals unchanged.

16. The method of claim 1 , further comprising:

generating an asynchronous netlist associated with the asynchronous circuit design, the asynchronous netlist to be applied to programming the asynchronous circuit design on a field-programmable gate array.

17. A method, comprising:

generating a synchronous netlist from a synchronous circuit design, the synchronous netlist including combinational logic gates and state-holding elements with multiple clock domains; and

converting the synchronous netlist to an asynchronous circuit design, wherein clock cycle times associated with at least some of the multiple clock domains are rational multiples of each other, and wherein the converting includes generating annotations by an annotation generator to map performance chartacteristics from the asychronous circuit design into the synchronous circuit design to validate timing characteristics of the asynchronous circuit design.

18. The method of claim 17 , further comprising:

determining a repeating period that corresponds to a least common multiple of the clock cycle times.