IP Library › Granted Patent US 8,467,890
Granted Patent B2
US 8,467,890 · App. 12/268,341 · Granted Jun 18, 2013

Method and system for detecting interrupts from detachable electronic accessories or peripherals

Inventors: Hongwei Kong (Denville, NJ); Liang Deng (San Jose, CA)
Assignee: Broadcom Corporation
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Quick Facts
Patent No.
US 8,467,890
App. No.
12/268,341
Granted
Jun 18, 2013
Kind
B2
Abstract

Aspects of a method and system for detecting interrupts from detachable electronic accessories or peripherals are provided. In this regard, a hardware audio CODEC may be operable to compare a voltage on one or more biased pins of an accessory or peripheral port to one or more reference voltages and filter one or more output signals generated from the comparison. When an accessory or peripheral is coupled to the accessory or peripheral port, interrupts from the accessory or peripheral may be detected based on results of the comparison and/or the filtering. An interrupt may be detected when the voltage on the one or more pins may be below the one or more reference voltages. An interrupt may be detected when the voltage on the one or more pins may be below the one or more reference voltages for a plurality of consecutive clock cycles.

Claims (24)

1. A method for processing signals, the method comprising:

comparing, in a hardware audio CODEC, a voltage on one or more biased pins of an accessory or peripheral port to one or more reference voltages;

filtering, in said hardware audio CODEC, one or more output signals generated from said comparison based on a characteristic of an accessory or peripheral attached to said accessory or peripheral port; and

when said accessory or peripheral is coupled to said accessory or peripheral port, detecting an interrupt from said accessory or peripheral based on results of said comparison or said filtering.

2. The method according to claim 1 , comprising biasing, via said hardware audio CODEC, said one or more pins of said accessory or peripheral port via said hardware audio CODEC.

3. The method according to claim 2 , comprising applying, via said hardware audio CODEC, said voltage to each of said one or more pins via one or more resistances.

4. The method according to claim 1 , wherein said characteristic comprises a class, type, manufacturer identifier, or model identifier of said accessory or peripheral attached to said accessory or peripheral port.

5. The method according to claim 1 , comprising interpreting a state or behavior of said one or more output signals generated from said comparison based on said characteristic of said accessory or peripheral attached to said accessory or peripheral port.

6. The method according to claim 1 , comprising interpreting a state or behavior of said filtered one or more signals based on said characteristic of said accessory or peripheral attached to said accessory or peripheral port.

7. The method according to claim 1 , comprising filtering, in said hardware audio CODEC, said one or more output signals generated from said comparison via one or more filters configured into an integrate-and-dump mode of operation.

8. The method according to claim 1 , comprising filtering, in said hardware audio CODEC, said one or more output signals generated from said comparison via one or more filters configured into a decimate-by-M mode of operation.

9. The method according to claim 1 , comprising detecting said interrupt when said voltage on said one or more biased pins is below said one or more reference voltages.

10. The method according to claim 1 , comprising detecting said interrupt when said voltage on said one or more biased pins is below said one or more reference voltages for a plurality of consecutive clock cycles.

11. A system for processing signals, the system comprising:

one or more circuits for use in a hardware audio CODEC configured to compare a voltage on one or more biased pins of an accessory or peripheral port to one or more reference voltages and to filter one or more output signals that are generated from said comparison based on a characteristic of said accessory or peripheral attached to said accessory or peripheral port, wherein an interrupt from said accessory or peripheral is detected based on results of said comparison or said filtering when said accessory or peripheral is coupled to said accessory or peripheral port.

12. The system according to claim 11 , wherein said one or more circuits are configured to bias said one or more pins of said accessory or peripheral port.

13. The system according to claim 12 , wherein said one or more circuits are configured to apply said voltage to each of said one or more pins via one or more resistances.

14. The system according to claim 11 , wherein said characteristic comprises a class, type, manufacturer identifier, or model identifier of said accessory or peripheral attached to said accessory or peripheral port.

15. The system according to claim 11 , wherein a state or behavior of said one or more output signals generated from said comparison is interpreted based on said characteristic of said accessory or peripheral attached to said accessory or peripheral port.

16. The system according to claim 11 , wherein a state or behavior of said filtered one or more signals is interpreted based on said characteristic of said accessory or peripheral attached to said accessory or peripheral port.

17. The system according to claim 11 , wherein said one or more circuits comprise a filter configured into an integrate-and-dump mode of operation.

18. The system according to claim 11 , wherein said one or more circuits comprise a filter configured into a decimate-by-M mode of operation.

19. The system according to claim 11 , wherein said interrupt is detected when said voltage on said one or more biased pins is below said one or more reference voltages.

20. The system according to claim 11 , wherein said interrupt is detected when said voltage on said one or more biased pins is below said one or more reference voltages for a plurality of consecutive clock cycles.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 09/05/2018 PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0133. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0456 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0133 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 6, 2009
From: KONG, HONGWEI; DENG, LIANG
To: BROADCOM CORPORATION
Reel/Frame 022356/0933 →
Continuity (1)
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