High density chip packages, methods of forming, and systems including same
Methods and devices for multi-chip stacks are shown. A method is shown that assembles multiple chips into stacks by stacking wafers prior to dicing into individual chips. Methods shown provide removal of defective chips and their replacement during the assembly process to improve manufacturing yield.
1. A semiconductor wafer assembly, comprising:
a redistribution plane wafer layer, including a number of chip sized regions in an array; and
a second wafer layer attached to the redistribution plane wafer layer, including a number of semiconductor chips in an array substantially matching the array of chip sized regions, wherein selected semiconductor chips from the number of semiconductor chips have been removed from the surface of the first wafer layer.
2. The semiconductor wafer assembly of claim 1 , wherein the number of chip sized regions includes memory chip sized regions.
3. The semiconductor wafer assembly of claim 1 , wherein the number of semiconductor chips includes logic chips.
4. The semiconductor wafer assembly of claim 1 , wherein the number of semiconductor chips includes memory chips.
5. A semiconductor wafer assembly, comprising:
a first wafer, including only redistribution circuitry; and
a second wafer attached to the first wafer, including a number of flash memory chips, wherein selected chips from the number of flash memory chips have been removed from the surface of the first wafer.
6. The semiconductor wafer assembly of claim 5 , wherein the chips in the second wafer are attached to the first wafer using controlled chip collapse connections (C4).
7. The semiconductor wafer assembly of claim 5 , wherein the chips in the second wafer are attached to the first wafer using TiNiCuAu pad metallurgy.
8. A multi-chip stack, comprising:
an end chip that includes only redistribution circuitry;
a plurality of chips stacked on the end chip, including:
at least one memory chip; and
at least one logic chip.
9. The multi-chip stack of claim 8 , wherein the at least one memory chip includes a dynamic random access memory (DRAM) chip.
10. The multi-chip stack of claim 8 , wherein the at least one memory chip includes a flash memory chip.
11. The multi-chip stack of claim 8 , wherein a second end chip, opposite the end chip that includes only redistribution circuitry is thicker than other chips in the plurality of chips.
12. The multi-chip stack of claim 8 , wherein the plurality of chips are interconnected using both chip edge connections and through chip connections.
13. An electronic system, comprising:
a multi-chip stack, including:
an end chip that includes only redistribution circuitry;
a plurality of chips stacked on the end chip, including:
at least one memory chip; and
at least one logic chip
a cooling system, coupled to the multi-chip stack to flow a cooling fluid through at least one gap at an interface between at least two chips in the plurality of chips.
14. The electronic system of claim 13 , wherein the fluid includes a liquid.
15. The electronic system of claim 13 , wherein the fluid includes a supercritical fluid.
16. The electronic system of claim 15 , wherein the supercritical fluid includes carbon dioxide.
17. The electronic system of claim 13 , wherein the fluid includes a pressurized gas.
18. The electronic system of claim 17 , wherein the pressurized gas includes hydrogen.
19. The electronic system of claim 17 , wherein the pressurized gas includes helium.
20. The electronic system of claim 17 , wherein the pressurized gas includes both hydrogen and helium.