Method for manufacturing an antifuse memory cell
A method for forming a memory cell including a selection transistor and an antifuse transistor, in a technological process adapted to the manufacturing of a first and of a second types of MOS transistors of different gate thicknesses, this method including the steps of: forming the selection transistor according to the steps of manufacturing of the N-channel transistor of the second type; and forming the antifuse transistor essentially according the steps of manufacturing of the N-channel transistor of the first type, by modifying the following step: instead of performing a P-type implantation in the channel region at the same time as in the N-channel transistors of the first type, performing an N-type implantation in the channel region at the same time as in the P-channel transistors of the first type.
1. A method for forming a memory cell comprising a selection MOS transistor ( 11 ) and an antifuse MOS transistor, from standard elementary cells of a technological process, these cells corresponding respectively to a first type of MOS transistors (NMOSGO 1 , PMOSGO 1 ) of a first gate thickness (e 1 ), adapted to implement logic functions of integrated circuits, and to a second type of MOS transistors (NMOSGO 2 ) of a second gate thickness (e 2 ) greater than the first thickness, adapted to implement power functions of integrated circuits, this method comprising the steps of:
forming the selection transistor according to the steps of manufacturing of an N-channel transistor of the second type (NMOSGO 2 ); and
forming the antifuse transistor essentially according to the steps of manufacturing an N-channel transistor of the first type (NMOSGO 1 ), by modifying the following step: instead of performing a P-type implantation in the channel region at the same time as in the N-channel transistors of the first type (NMOSGO 1 ), performing an N-type implantation in the channel region ( 27 PGO 1 ) at the same time as in the P-channel transistors of the first type (PMOSGO 1 ), wherein the antifuse transistor comprises the modified channel region of opposite implantation type to the channel region of the N-channel transistor of the first type (NMOSGO 1 ).
2. The method of claim 1 , wherein the steps of manufacturing of the antifuse transistor ( 13 ) further comprise the following modification: instead of forming the bulk well at the same time as in the N-channel transistors of the first type (NMOSGO 1 ), forming the bulk well (PWellGO 2 ) at the same time as in the N-channel transistors of the second type (NMOSGO 2 ).
3. The method of claim 1 , wherein the transistors of the first type (NMOSGO 1 , PMOSGO 1 ) are transistors of minimum dimensions of the technological process.
4. The method of claim 1 , wherein the source ( 18 NGO 1 ) and drain ( 19 NGO 1 ) regions of the N-channel transistor of the first type (NMOSGO 1 ) comprise more lightly doped portions ( 22 NGO 1 ) close to the gate.
5. The method of claim 4 , wherein the steps of manufacturing of the antifuse transistor ( 13 ) further comprise the following modification: instead of forming the more lightly-doped source and drain portions at the same time as in the N-channel transistors of the first type (NMOSGO 1 ), forming the more lightly-doped source and drain portions ( 22 N) at the same time as in the N-channel transistors of the second type (NMOSGO 2 ).
6. The method of claim 1 , wherein the N-channel transistors of the first type (NMOSGO 1 ) comprise insulating spacers ( 24 GO 1 ) on either side of the gate.
7. The method of claim 1 , wherein the N-channel transistors of the first type (NMOSGO 1 ) comprise P-type pockets ( 26 NGO 1 ) arranged on either side of the gate, around a portion of the source and drain regions, and wherein the antifuse transistor ( 13 ) does not comprise P-type pockets around the source and drain regions.