Controlling power consumption in iterative ECC processing systems

1. A system, comprising:

an iterative error correction coding (ECC) decoder; and

a controller configured to:

configure the iterative ECC decoder to operate in a first higher-power and higher-performance operating mode;

monitor at least some part of a system that includes the iterative ECC decoder;

decide whether to switch the iterative ECC decoder from the first higher-power and higher-performance operating mode to a second lower-power and lower-performance operating mode based at least in part on the monitoring; and

configure the iterative ECC decoder to operate in the second lower-power and lower-performance operating mode in the event the controller decides to switch operating modes.

2. The system recited in claim 1 , wherein:

monitoring includes using a temperature sensor; and

deciding is based at least in part on temperature information from the temperature sensor.

3. The system recited in claim 1 , wherein:

monitoring includes obtaining status information from the iterative ECC decoder; and

deciding is based at least in part on the status information.

4. The system recited in claim 1 , wherein the iterative ECC decoder includes a low-density parity-check (LDPC) decoder.

5. The system recited in claim 1 further comprising:

a soft output Viterbi decoder; and

storage, wherein the soft output Viterbi decoder and the iterative ECC decoder are configured to exchange data via the storage.

6. The system recited in claim 5 , wherein:

monitoring includes obtaining a first number of iterations that the soft output Viterbi decoder operated for and obtaining a second number of iterations that the iterative ECC decoder operated for; and

deciding is based at least in part on the first number of iterations and the second number of iterations.

7. The system recited in claim 6 , wherein the first number of iterations and the second number of iterations are a number of iterations that the soft output Viterbi decoder and the iterative ECC decoder, respectively, operated on a same sector from a disk storage device.

8. The system recited in claim 5 , wherein configuring the iterative ECC decoder to operate in a second lower-power and lower-performance operating mode includes reducing a first maximum number of iterations that the soft output Viterbi decoder can operate for and/or reducing a second maximum number of iterations that the iterative ECC decoder can operate for.

9. The system recited in claim 1 , wherein configuring the iterative ECC decoder to operate in a second lower-power and lower-performance operating mode includes reducing a maximum number of iterations that the iterative ECC decoder can operate for.

10. The system recited in claim 1 , wherein the controller is further configured to:

decide whether to return the iterative ECC decoder to the first higher-power and higher-performance operating mode; and

configure the iterative ECC decoder to operate in the first higher-power and higher-performance operating mode in the event the controller decides to return the iterative ECC decoder to the first higher-power and higher-performance operating mode.

11. A method, comprising:

using a processor to configure an iterative error correction coding (ECC) decoder to operate in a first higher-power and higher-performance operating mode;

monitoring at least some part of a system that includes the iterative ECC decoder;

using the processor to decide whether to switch the iterative ECC decoder from the first higher-power and higher-performance operating mode to a second lower-power and lower-performance operating mode based at least in part on the monitoring; and

using the processor to configure the iterative ECC decoder to operate in the second lower-power and lower-performance operating mode in the event the processor decides to switch operating modes.

12. The method recited in claim 11 , wherein:

monitoring includes using a temperature sensor; and

deciding is based at least in part on temperature information from the temperature sensor.

13. The method recited in claim 11 , wherein:

monitoring includes obtaining status information from the iterative ECC decoder; and

deciding is based at least in part on the status information.

14. The method recited in claim 11 , wherein the iterative ECC decoder includes a low-density parity-check (LDPC) decoder.

15. The method recited in claim 11 , wherein:

monitoring includes obtaining a first number of iterations that a soft output Viterbi decoder operated for and obtaining a second number of iterations that the iterative ECC decoder operated for; and

deciding is based at least in part on the first number of iterations and the second number of iterations.

16. The method recited in claim 15 , wherein the first number of iterations and the second number of iterations are a number of iterations that the soft output Viterbi decoder and the iterative ECC decoder, respectively, operated on a same sector from a disk storage device.

17. The method recited in claim 11 , wherein configuring the iterative ECC decoder to operate in a second lower-power and lower-performance operating mode includes reducing a maximum number of iterations that the iterative ECC decoder can operate for.

18. The method recited in claim 11 , wherein configuring the iterative ECC decoder to operate in a second lower-power and lower-performance operating mode includes reducing a first maximum number of iterations that a soft output Viterbi decoder can operate for and/or reducing a second maximum number of iterations that the iterative ECC decoder can operate for.

19. The method recited in claim 11 , further comprising:

using the processor to decide whether to return the iterative ECC decoder to the first higher-power and higher-performance operating mode; and

configuring the iterative ECC decoder to operate in the first higher-power and higher-performance operating mode in the event the processor decides to return the iterative ECC decoder to the first higher-power and higher-performance operating mode.

20. A computer program product, the computer program product being embodied in a non-transitory computer readable storage medium and comprising computer instructions for:

configuring an iterative error correction coding (ECC) decoder to operate in a first higher-power and higher-performance operating mode;

monitoring at least some part of a system that includes the iterative ECC decoder;

deciding whether to switch the iterative ECC decoder from the first higher-power and higher-performance operating mode to a second lower-power and lower-performance operating mode based at least in part on the monitoring; and

configuring the iterative ECC decoder to operate in the second lower-power and lower-performance operating mode in the event the computer instructions for deciding decide to switch operating modes.