Method and apparatus for improving sensitivity in vertical color CMOS image sensors
The invention describes in detail the structure of a CMOS image sensor pixel that senses color of impinging light without having absorbing filters placed on its surface. The color sensing is accomplished by having a vertical stack of three-charge detection nodes placed in the silicon bulk, which collect electrons depending on the depth of their generation. The small charge detection node capacitance and thus high sensitivity with low noise is achieved by using fully depleted, potential well forming, buried layers instead of undepleted junction electrodes. Two embodiments of contacting the buried layers without substantially increasing the node capacitances are presented.
1. A light-sensing pixel, having a p type doped region, in a CMOS image sensor, comprising:
a first doped charge collecting region buried within the p type doped region and configured to operate as a depleted potential well;
a first vertical trench transistor extending from near the surface of the image sensor to the first charge collecting region;
a first n+ type doped region located at the surface of the image sensor and coupled to the first vertical trench transistor;
a second doped charge collecting region buried within the p type doped region, the second charge collecting region vertically separated from the first charge collecting region by the p type doped region and configured to operate as a depleted potential well;
a second vertical trench transistor extending from near the surface of the image sensor to the second charge collecting region; and
a second n+ type doped region located at the surface of the image sensor and coupled to the second vertical trench transistor.
2. The pixel of claim 1 , the first and second charge collecting regions further comprising:
a first extension with n+ type doping coupled to and between the first charge collecting region and the first vertical trench transistor, and having a different doping concentration than the first charge collecting region; and
a second extension with n+ type doping coupled to and between the second charge collecting region and the second vertical trench transistor, and having a different doping concentration than the second charge collecting region.
3. The pixel of claim 2 wherein the first and second extensions are configured to operate not fully depleted of mobile charge.
4. The pixel of claim 1 wherein the first vertical trench transistor contacts the first charge collecting region in its center.