Entrenched transfer gate

1. A complementary metal-oxide semiconductor (“CMOS”) image sensor, comprising:

an epitaxial layer in or on which a pixel array is disposed, wherein a pixel cell of the pixel array includes:

a photodiode disposed within the epitaxial layer to accumulate photo-generated charge;

a floating node disposed within the epitaxial layer; and

an entrenched transfer gate disposed within the epitaxial layer between the photodiode and the floating diffusion to control transfer of the photo-generated charge from the photosensitive region to the floating node, wherein the entrenched transfer gate comprises:

a bottom portion disposed within a trench that extends into the epitaxial layer, the bottom portion having a trapezoidal shape with a long side facing the photodiode and a short side facing the floating node; and

a top portion having a rectangular shape disposed over the bottom portion that extends above a top surface of the epitaxial layer.

2. The CMOS image sensor of claim 1 , wherein the pixel cell further includes:

a P well disposed within the epitaxial layer adjacent to the entrench transfer gate, wherein the floating node is N doped and is at least partially disposed within the P well; and

a deep N type region disposed within the epitaxial layer below the photodiode,

wherein the P well and the deep N type region interface forming a P-N junction and the P well does not extend under the photodiode.

3. The CMOS image sensor of claim 1 , further comprising:

a gate oxide layer lining the trench and separating the entrenched transfer gate from the photodiode and the floating node;

a P well disposed within the epitaxial layer adjacent to the trench, wherein the floating node is N doped and is at least partially disposed within the P well;

a deep N type region disposed within the epitaxial layer below the photodiode; and

a P type punch-through stopper region disposed below the trench.

4. The CMOS image sensor of claim 3 , wherein the pixel array comprises a backside illuminated pixel array and wherein an interface between the P well and the deep N type region forms a p-n junction that resides offset from the entrenched transfer gate and below the floating node.

5. The CMOS image sensor of claim 1 , wherein the entrenched transfer gate comprises:

a first P doped portion; and

a second N doped portion,

wherein the first P doped portion is adjacent to the photodiode and the second N doped portion is adjacent to the floating node,

wherein the floating node comprises a first N doped region disposed within a P well,

wherein the photodiode comprises a second N doped region.

6. The CMOS image sensor of claim 5 , wherein the first P doped portion and the second N doped portion split the entrenched transfer gate along a line that extends substantially normal to a top surface of the epitaxial layer.

7. An image sensor pixel, comprising:

a semiconductor layer;

a photosensitive region disposed within the semiconductor layer to accumulate photo-generated charge;

a floating node disposed within the semiconductor layer;

a trench extending into the semiconductor layer between the photosensitive region and the floating node;

an entrenched transfer gate disposed within the trench to control transfer of the photo-generated charge from the photosensitive region to the floating node;

a well of a first polarity disposed within the semiconductor layer adjacent to the trench, wherein the floating node has a second polarity and is at least partially disposed within the well;

a deep doped region of the second polarity disposed within the semiconductor layer below the photosensitive region; and

an implant region of the first polarity disposed within the semiconductor layer and abutting the trench and extending beneath the floating node, wherein the implant region has a higher dopant concentration than the well.

8. The CMOS image sensor of claim 1 , further comprising:

a punch-through stopper region of the first polarity disposed below the entrenched transfer gate.