Semiconductor integrated circuit having a multi-chip structure
A semiconductor integrated circuit having a multi-chip structure includes a plurality of stacked semiconductor chips. At least one of the semiconductor chips includes first and second metal layers separately formed inside the semiconductor chip, a first internal circuit coupled in series between the first and second metal layers inside the semiconductor chip, a first metal path vertically formed over the second metal layer to a first side of the semiconductor chip, and a first through silicon via formed through the semiconductor chip from a second side of the semiconductor chip to the first metal layer.
1. A semiconductor integrated circuit having a multi-chip structure, comprising a plurality of stacked semiconductor chips, wherein at least one of the semiconductor chips comprises:
first and second metal layers separately formed inside the semiconductor chip;
a first internal circuit coupled in series between the first and second metal layers inside the semiconductor chip;
a first metal path vertically formed over the second metal layer to a first side of the semiconductor chip;
a first through silicon via formed through the semiconductor chip from a second side of the semiconductor chip to the first metal layer; and
a first bump pad formed over the semiconductor chip to couple a first through silicon via of another semiconductor chip and the first metal path of the semiconductor chip.
2. The semiconductor integrated circuit of claim 1 , wherein
the first bump pad is formed at substantially the same column region as first through silicon via.
3. The semiconductor integrated circuit of claim 1 , wherein the first internal circuit and the first through silicon via of the semiconductor chip are coupled in series to the first internal circuit and the first trough electrode of another semiconductor chip.
4. The semiconductor integrated circuit of claim 1 , wherein the semiconductor chip further comprises:
a third metal layer formed to be separate from the first and second metal layers;
a second internal circuit coupled in parallel to the third metal layer;
a second metal path vertically formed over the third metal layer to the first side of the semiconductor chip;
a second through silicon via formed through the semiconductor chip from the second side of the semiconductor chip up to the third metal layer; and
a second bump pad formed to couple a second through silicon via of another semiconductor chip and the second metal path of the semiconductor chip.
5. The semiconductor integrated circuit of claim 4 , wherein the second through silicon via of the semiconductor chip are coupled in series to the second through silicon via of another semiconductor chip.
6. The semiconductor integrated circuit of claim 4 , wherein the second bump pad is formed at the same column region as the second through silicon via.
7. The semiconductor integrated circuit of claim 6 , wherein the first through silicon via and the first bump pad are symmetrical with the second through silicon via and the second bump pad.
8. The semiconductor integrated circuit of claim 4 , wherein each of the first and second metal paths comprises a plurality of metal lines and a plurality of metal contacts arranged between the respective metal lines.
9. The semiconductor integrated circuit of claim 4 , wherein each of the first and second metal paths is formed of one via.