Semiconductor device and method of manufacturing the same

1. A semiconductor device, comprising:

a semiconductor substrate;

first and second impurity diffusion regions formed on the semiconductor substrate so that a top surface of the semiconductor substrate is defined by a space between the first and second impurity regions;

a semiconductor pillar projecting from the top surface of the semiconductor substrate;

a third impurity diffusion region formed on a top portion of the semiconductor pillar;

a gate insulating film having a first main surface contacting a side surface of the semiconductor pillar and the first and second impurity diffusion regions, the first main surface further contacting a lower portion of a sidewall of the third impurity diffusion region so that an upper portion other than the lower portion of the sidewall of the third impurity diffusion region is not covered with the gate insulating film;

a gate electrode formed on a second main surface of a lower portion of the gate insulating film so that an upper portion other than the lower portion of the gate insulating film is not covered with the gate electrode, the second main surface opposing to the first main surface; and

a contact plug contacting a top surface and the upper portion of the side wall of the third impurity diffusion region and an end of the gate insulating film.

2. The semiconductor device as claimed in claim 1 , further comprising:

a first insulation layer contacting the gate electrode, the upper portion of the gate insulating film and the contact plug.

3. The semiconductor device as claimed in claim 2 , further comprising:

a second insulation layer formed on the first insulating layer and contacting the contact plug, the second insulation layer being different in material from the first insulation layer; and

a capacitor contacting the contact plug and the second insulation layer.

4. A semiconductor device, comprising:

a semiconductor member;

first and second impurity diffusion regions formed on the semiconductor member so that a top surface of the semiconductor member is defined by a space between the first and second impurity regions;

a semiconductor portion formed on the top surface of the semiconductor substrate;

a third impurity diffusion region formed on a top portion of the semiconductor portion;

a gate insulating film having a first main surface contacting a side surface of the semiconductor portion and the first and second impurity diffusion regions, the first main surface further contacting a lower portion of a sidewall of the third impurity diffusion region so that an upper portion other than the lower portion of the sidewall of the third impurity diffusion region is not covered with the gate insulating film;

a gate electrode formed on a second main surface of a lower portion of the gate insulating film so that an upper portion other than the lower portion of the gate insulating film is not covered with the gate electrode, the second main surface opposing to the first main surface; and

a contact plug contacting a top surface and the upper portion of the side wall of the third impurity diffusion region and an end of the gate insulating film.

5. The semiconductor device as claimed in claim 4 , further comprising:

a first insulation layer contacting the gate electrode, the upper portion of the gate insulating film and the contact plug.

6. The semiconductor device as claimed in claim 5 , further comprising:

a second insulation layer formed on the first insulating layer and contacting the contact plug, the second insulation layer being different in material from the first insulation layer; and

a capacitor contacting the contact plug and the second insulation layer.

7. A semiconductor device, comprising:

a semiconductor member;

a first semiconductor portion formed on the semiconductor member;

a second semiconductor portion formed on the semiconductor member and apart from the first semiconductor portion in a first direction with a first distance;

a third semiconductor portion formed on the semiconductor member and apart from the first semiconductor portion in a second direction perpendicular to the first direction with a second distance smaller than the first distance;

an impurity diffusion region formed on a top portion of the first, second and third semiconductor portions;

a gate insulating film having a first main surface contacting a side surface of the first, second and third semiconductor portions, the first main surface further contacting a lower portion of a sidewall of the impurity diffusion region so that an upper portion other than the lower portion of the sidewall of the impurity diffusion region is not covered with the gate insulating film;

a gate electrode formed on a second main surface of a lower portion of the gate insulating film so that an upper portion other than the lower portion of the gate insulating film is not covered with the gate electrode, the second main surface opposing to the first main surface, the gate electrode including first and second gate electrode portions provided between the first and second semiconductor portions and separated from each other, the gate electrode further including a third gate electrode portion continuously provided from the first semiconductor portion to the third semiconductor portion;

first to third contact plugs provided over the first to third semiconductor portions respectively, the first to third contact plugs contacting a top surface and the upper portion of the side wall of the impurity diffusion region and an end of the gate insulating film; and

a first insulating layer formed between the first and second contact plugs so as to be provided between the first and second gate electrode portions, the first insulating layer further being formed between the first and third contact plugs so as to be provided on the third gate electrode portion.

8. The semiconductor device as claimed in claim 7 , further comprising:

a second insulating layer formed on the first insulating layer, the second insulating layer being provided between the first and second contact plugs and between the first and third contact plugs, the second insulation layer being different in material from the first insulation layer.

9. The semiconductor device as claimed in claim 8 , further comprising;

first to third capacitors formed on the first to third contact plugs, respectively.