Stacked integrated chips and methods of fabrication thereof

1. A method of forming a semiconductor chip, the method comprising:

forming an opening for a through substrate via from a top surface of a first substrate;

lining sidewalls of the opening with an insulating liner;

filling the opening with a conductive fill material;

etching the first substrate from an opposite bottom surface to form a protrusion, the protrusion being covered with the insulating liner;

depositing a resist layer around the protrusion to expose a portion of the insulating liner;

etching the exposed insulating liner to form a sidewall spacer along the protrusion; and

replacing the resist layer with an under-fill layer, the under-fill layer directly adjoining the sidewall spacer.

2. The method of claim 1 , wherein a thickness of the resist layer is thinner than a height of the protrusion, and wherein a height of the sidewall spacer along the protrusion is about the same as the thickness of the resist layer.

3. The method of claim 1 , wherein a height of the sidewall spacer along the protrusion is less than a height of the protrusion.

4. The method of claim 1 , further comprising:

flipping the first substrate after filling the opening with the conductive fill material; and

removing the resist layer after etching the exposed insulating liner.

5. The method of claim 1 , wherein the first substrate comprises a semiconductor wafer comprising active circuitry on the top surface, and wherein the opening extends from the top surface to a lower surface disposed within the first substrate.

6. The method of claim 1 , wherein etching the insulating liner comprises using a wet etch chemistry to remove the insulating liner without removing the resist layer.

7. The method of claim 1 , wherein the insulating liner comprises a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, SiC, SiCN, a low k dielectric material, a ultra low k dielectric material, and combinations thereof, wherein the conductive fill material comprises a material selected from the group consisting of copper, aluminum, tungsten, silver, gold, doped polysilicon, and combinations thereof, and wherein the resist layer comprises a photo resist or an antireflective coating material.

8. The method of claim 1 , further comprising:

forming a wetting layer on the conductive fill material of the protrusion; and

forming a solder ball joint to electrically couple active circuitry on the first substrate to active circuitry on a second substrate.

9. The method of claim 8 , wherein the wetting layer comprises a nickel/gold layer formed using an electroless plating process.

10. A method of forming a semiconductor chip, the method comprising:

forming an opening for a through substrate via from a top side of a first substrate;

lining sidewalls of the opening with an insulating liner;

filling the opening with a conductive fill material;

etching the first substrate from an opposite bottom side to expose a portion of the insulating liner disposed on the sidewalls of the opening;

depositing a resist layer from the bottom side to expose a region of the exposed insulating liner;

etching the region of the exposed insulating liner;

after the etching the region of the exposed insulating liner, removing the resist layer to expose sidewalls of the insulating liner; and

depositing a polymer layer on the bottom side, the polymer layer directly adjoining the exposed sidewalls of the insulating liner and directly adjoining exposed sidewalls of the conductive fill material.

11. The method of claim 10 , further comprising:

forming a wetting layer on the conductive fill material from the bottom side, wherein the wetting layer comprises forming a nickel/gold layer formed using an electroless plating process; and

forming a solder ball joint to electrically couple active circuitry on the first substrate to active circuitry on a second substrate.

12. The method of claim 10 , wherein the opening extends from the top side to a lower surface disposed within the first substrate.

13. The method of claim 10 , wherein etching the region of the exposed insulating liner comprises using a wet etch chemistry to remove the insulating liner without removing the resist layer.

14. The method of claim 10 , wherein the insulating liner comprises a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, SiC, SiCN, a low k dielectric material, a ultra low k dielectric material, and combinations thereof, wherein the conductive fill material comprises a material selected from the group consisting of copper, aluminum, tungsten, silver, gold, doped polysilicon, and combinations thereof, and wherein the resist layer comprises a photo resist or an antireflective coating material.

15. A method of forming a semiconductor chip, the method comprising:

forming an opening for a through substrate via from a top surface of a first substrate;

lining sidewalls of the opening with an insulating liner;

filling the opening with a conductive fill material;

etching the first substrate from an opposite bottom surface to expose a portion of the insulating liner;

depositing a resist layer around the exposed portion of the insulating liner;

forming a sidewall spacer on the conductive fill material on a first part of the exposed portion of the insulating liner by removing the remaining part of the exposed portion of the insulating liner using a wet etch process; and

replacing the resist layer with an under-fill layer, the under-fill layer contacting a sidewall of the sidewall spacer and contacting a sidewall of the conductive fill material.

16. The method of claim 15 , further comprising removing the resist layer after removing the remaining part of the exposed portion of the insulating liner.

17. The method of claim 15 , further comprising:

forming a wetting layer on the conductive fill material adjacent the sidewall spacer, wherein the wetting layer comprises forming a nickel/gold layer formed using an electroless plating process; and

forming a solder ball joint to electrically couple active circuitry on the first substrate to active circuitry on a second substrate.

18. The method of claim 15 , wherein the opening extends from the top surface to a lower surface disposed within the first substrate.

19. The method of claim 15 , wherein etching the region of the exposed insulating liner comprises using a wet etch chemistry to remove the insulating liner without removing the resist layer.

20. The method of claim 15 , wherein the insulating liner comprises a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, SiC, SiCN, a low k dielectric material, a ultra low k dielectric material, and combinations thereof, wherein the conductive fill material comprises a material selected from the group consisting of copper, aluminum, tungsten, silver, gold, doped polysilicon, and combinations thereof, and wherein the resist layer comprises a photo resist or an antireflective coating material.