Self-aligned protection layer for copper post structure

1. A semiconductor device, comprising:

a semiconductor substrate;

a conductive post overlying and electrically connected to the substrate; and

a manganese-containing protection layer on a surface of the conductive post.

2. The semiconductor device of claim 1 , wherein the manganese-containing protection layer is a self-aligned protection layer.

3. The semiconductor device of claim 1 , further comprising a conductive region formed in the substrate configured to electrically connect the substrate to the conductive post.

4. The semiconductor device of claim 3 , further comprising a post-passivation interconnect line configured to electrically connect the conductive region and the conductive post.

5. The semiconductor device of claim 1 , further comprising an under bump metallurgy (UBM) layer between the substrate and the conductive post.

6. The semiconductor device of claim 5 , wherein the manganese-containing protection layer covers sidewalls of the conductive post and sidewalls of the UBM layer.

7. A method of forming a semiconductor device, the method comprising:

forming a bond pad region on a semiconductor substrate;

forming a conductive post overlying and electrically connected to the bond pad region; and

forming a protection layer on a surface of the conductive post, wherein the protection layer comprises manganese (Mn).

8. The method of claim 7 , wherein forming the conductive post comprises forming the conductive post containing an alloy comprising manganese.

9. The method of claim 8 , wherein forming the protection layer comprises annealing the alloy conductive post to diffuse the manganese in the alloy conductive post to the surface of the conductive post.

10. The method of claim 9 , wherein annealing the alloy conductive post comprises annealing the alloy conductive post in an environment containing at least one of NH 3 or N 2 , and the protection layer comprises manganese nitride.

11. The method of claim 9 , wherein forming the conductive post comprises forming a copper-manganese alloy post, and annealing the copper-manganese alloy conductive post comprises reducing copper oxide and forming manganese oxide.

12. The method of claim 7 , further comprising forming a post-passivation interconnect line to electrically connect the conductive post to the bond pad.

13. The method of claim 7 , further comprising forming an under bump metallurgy (UBM) layer between the bond pad and the conductive post, wherein the protection layer covers sidewalls of the conductive post and the UBM layer.

14. A method of forming a semiconductor device, the method comprising:

forming a bond pad region on a semiconductor substrate;

forming a conductive post overlying and electrically connected to the bond pad region, the conductive post comprising a copper-manganese alloy; and

forming a manganese-containing protection layer on sidewalls of the conductive post.

15. The method of claim 14 , wherein forming the manganese-containing protection layer comprises annealing the copper-manganese alloy of the conductive post.

16. The method of claim 15 , wherein annealing the copper-manganese alloy comprises annealing the copper-manganese alloy in an environment containing at least one of NH 3 or N 2 , to form a self-aligned manganese nitride protection layer.

17. The method of claim 14 , further comprising forming the manganese-containing protection layer over a top surface of the conductive post.

18. The semiconductor device of claim 1 , further comprising a copper alloy layer between the substrate and the conductive post.

19. The semiconductor device of claim 18 , wherein the copper alloy layer includes a gradient manganese concentration.

20. The method of claim 7 , further comprising forming a copper alloy layer between the bond pad region and the conductive post.