IP Library › Granted Patent US 8,501,628
Granted Patent B2
US 8,501,628 · App. 12/729,538 · Granted Aug 6, 2013

Differential metal gate etching process

Inventors: Vinh Hoang Luong (Boise, ID); Hiroyuki Takahashi (Tokyo, JP); Akiteru Ko (Schenectady, NY); Asao Yamashita (Tokyo, JP); Vaidya Bharadwaj (Austin, TX); Takashi Enomoto (Rensselaer, NY); Daniel J. Prager (Hopewell Junction, NY)
Assignee: Tokyo Electron Limited
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Quick Facts
Patent No.
US 8,501,628
App. No.
12/729,538
Granted
Aug 6, 2013
Kind
B2
Abstract

A method for etching a differential metal gate structure on a substrate is described. The differential metal gate structure includes a metal gate layer overlying a high dielectric constant (high-k) dielectric layer, wherein the metal gate layer comprises a different thickness at different regions on the substrate. The metal gate layer is patterned by using a plasma etching process, wherein at least one etch step includes forming plasma using a halogen-containing gas and at least one etch step includes forming plasma using an additive gas having as atomic constituents C, H, and F.

Claims (29)

1. A method for performing a differential metal gate etching process, comprising:

disposing a substrate in a plasma processing system, said substrate having a differential metal gate structure including a metal gate layer overlying a high dielectric constant (high-k) dielectric layer, wherein said metal gate layer comprises a first thickness for a first region on said substrate and a second thickness for a second region on said substrate, said second thickness being greater than said first thickness; and

performing a differential metal gate etching process for pattern etching said metal gate layer through said first thickness at said first region and said second thickness at said second region, wherein said differential metal gate etching process comprises at least one etch step that includes forming plasma using a halogen-containing gas and at least one etch step that includes forming plasma using an additive gas having C, H, and F as atomic constituents.

2. The method of claim 1 , wherein said first thickness of said metal gate layer at said first region corresponds to an nFET device, and said second thickness of said metal gate layer at said second region corresponds to a pFET device.

3. The method of claim 1 , wherein said metal gate layer comprises one or more elements selected from the group consisting of Ti, Ta, and Al, and said high-k dielectric layer comprises one or more elements selected from the group consisting of Hf and La.

4. The method of claim 1 , wherein said metal gate layer comprises titanium nitride, and said high-k dielectric layer comprises hafnium dioxide (HfO 2 ), hafnium silicate (HfSiO), or nitrided hafnium silicate (HfSiO(N)), or any combination of two or more thereof.

5. The method of claim 1 , wherein said halogen-containing gas includes one or more gases selected from the group consisting of Cl 2 , HBr, and BCl 3 .

6. The method of claim 1 , wherein said additive gas includes one or more gases selected from the group consisting of CH 2 F 2 and CHF 3 .

7. The method of claim 1 , wherein said differential metal gate etching process comprises:

performing a first etch step that includes pattern etching said metal gate layer using plasma formed from a process composition containing a halogen-containing gas; and

following said first etch step, performing a selective etch step that includes pattern etching said metal gate layer using plasma formed from a process composition containing a halogen-containing gas and an additive gas having the chemical formula C x H y F z , where x, y and z are equal to unity or greater.

8. The method of claim 7 , wherein said first etch step proceeds for a time duration sufficient to etch through said metal gate layer for at least a portion of said first region, and said selective etch step proceeds for a time duration sufficient to fully complete said pattern etching of said metal gate layer for said first region and said second region.

9. The method of claim 7 , wherein said time duration for said first etch step is determined in-situ using endpoint detection and said time duration for said selective etch step is determined prior to performing said selective etch step.

10. The method of claim 7 , wherein said selective etch step proceeds at a process pressure greater than said first etch step.

11. The method of claim 7 , wherein said first etch step utilizes plasma formed of a process composition containing Cl 2 , and said selective etch step utilizes plasma formed of a process composition containing Cl 2 and CHF 3 .

12. The method of claim 11 , wherein said process composition in said first etch step and said selective etch step further include N 2 and Ar.

13. The method of claim 7 , further comprising:

following said first etch step, and either preceding or following said selective etch step, performing a second etch step that includes pattern etching said metal gate layer using plasma formed from a process composition containing a halogen-containing gas.

14. The method of claim 13 , wherein said first etch step proceeds for a time duration sufficient to etch through said metal gate layer for at least a portion of said first region, said selective etch step proceeds for a time duration sufficient to fully complete said pattern etching of said metal gate layer for said first region, and said second etch step follows said selective etch step and proceeds for a time duration sufficient to fully complete said pattern etching of said metal gate layer for said second region.

15. The method of claim 13 , wherein said first etch step proceeds for a time duration sufficient to etch through said metal gate layer for at least a portion of said first region, said second etch step precedes said selective etch step and proceeds for a time duration sufficient to complete said pattern etching of said metal gate layer for said first region and at least a portion of said second region, and said selective etch step proceeds for a time duration sufficient to fully complete said pattern etching of said metal gate layer for said first region and said second region.

16. The method of claim 13 , wherein said time duration for said first etch step is determined in-situ using endpoint detection, said time duration for said second etch step is determined prior to performing said second etch step, and said time duration for said selective etch step is determined prior to performing said selective etch step.

17. The method of claim 13 , wherein said first etch step utilizes plasma formed of a process composition containing Cl 2 , said second etch step utilizes plasma formed of a process composition containing Cl 2 , and said selective etch step utilizes plasma formed of a process composition containing Cl 2 and CHF 3 .

18. The method of claim 17 , wherein said process composition in said first etch step, said second etch step, and said selective etch step further include N 2 and Ar.

19. A method for performing a differential metal gate etching process, comprising:

disposing a substrate in a plasma processing system, said substrate having a differential metal gate structure including a metal gate layer overlying a high dielectric constant (high-k) dielectric layer, wherein said metal gate layer comprises a first thickness for a first region on said substrate and a second thickness for a second region on said substrate, said second thickness being greater than said first thickness;

performing a differential metal gate etching process for pattern etching said metal gate layer through said first thickness at said first region and said second thickness at said second region using a plurality of etch steps; and

substantially eliminating a footing in said metal gate layer at said second region by introducing an additive gas having C, H, and F as atomic constituents to at least one etch step in said plurality of etch steps.

20. The method of claim 19 , further comprising:

substantially eliminating silicon damage to a silicon-containing layer underlying said high-k dielectric layer at said first region.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 21, 2011
From: BHARADWAJ, VAIDYA
To: TOKYO ELECTRON LIMITED
Reel/Frame 025992/0114 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 23, 2010
From: LUONG, VINH HOANG; TAKAHASHI, HIROYUKI; KO, AKITERU; YAMASHITA, ASAO; BALASUBRAMANIAM, VAIDYANATHAN; ENOMOTO, TAKASHI; PRAGER, DANIEL J.
To: TOKYO ELECTRON LIMITED
Reel/Frame 024123/0333 →
Continuity (1)
Related Publication 20110237084A1 · Sep 29, 2011