Chip package and method for forming the same
View Patent ↗An embodiment of the invention provides a chip package which includes: a carrier substrate; a semiconductor substrate having an upper surface and a lower surface, disposed overlying the carrier substrate; a device region or sensing region located on the upper surface of the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.
1. A method for forming a chip package comprising:
providing a semiconductor substrate having an upper surface and a lower surface, wherein the semiconductor substrate comprises at least a device region or sensing region and at least a conducting pad on the upper surface of the semiconductor substrate;
providing a carrier substrate and disposing the semiconductor substrate overlying the carrier substrate;
forming a recess from the upper surface of the semiconductor substrate;
thinning the semiconductor substrate before the recess is formed;
forming an insulating layer overlying the upper surface of the semiconductor substrate and within the recess;
forming a conducting layer overlying the insulating layer, wherein the conducting layer is electrically connected to the conducting pad and extends from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and
dicing the carrier substrate from a bottom of the recess to form a plurality of separate chip packages.
2. The method for forming a chip package as claimed in claim 1 , wherein the step of thinning the semiconductor substrate comprises:
disposing a temporary substrate overlying the upper surface of the semiconductor substrate before the semiconductor substrate is disposed overlying the carrier substrate; and
thinning the semiconductor substrate from the lower surface of the semiconductor substrate by using the temporary substrate as a support.
3. The method for forming a chip package as claimed in claim 2 , further comprising removing the temporary substrate before the recess is formed.
4. The method for forming a chip package as claimed in claim 1 , further comprising:
providing a circuit board having a contact pad;
disposing the carrier substrate overlying the circuit board; and
forming a conducting structure, wherein the conducting structure is electrically connected to the contact pad and the conducting layer.
5. The method for forming a chip package as claimed in claim 4 , wherein the conducting structure comprises a solder ball or a solder wire.
6. The method for forming a chip package as claimed in claim 5 , wherein the conducting structure is a solder ball, and the solder ball is located on a corner between the carrier substrate and the circuit board.
7. The method for forming a chip package as claimed in claim 1 , wherein the device region or sensing region is substantially and directly exposed.
8. A method for forming a chip package, comprising:
providing a semiconductor substrate having an upper surface and a lower surface, wherein the semiconductor substrate comprises at least a device region or sensing region and at least a conducting pad on the upper surface of the semiconductor substrate;
providing a carrier substrate and disposing the semiconductor substrate overlying the carrier substrate;
forming a recess from the upper surface of the semiconductor substrate;
forming an insulating layer overlying the upper surface of the semiconductor substrate and within the recess;
forming a conducting layer overlying the insulating layer, wherein the conducting layer is electrically connected to the conducting pad and extends from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate, and wherein the conducting layer extends on the bottom of the recess; and
dicing the carrier substrate from a bottom of the recess to form a plurality of separate chip packages.
9. The method for forming a chip package as claimed in claim 8 , further comprising:
providing a circuit board having a contact pad;
disposing the carrier substrate overlying the circuit board; and
forming a conducting structure, wherein the conducting structure is electrically connected to the contact pad and the conducting layer.
10. The method for forming a chip package as claimed in claim 9 , wherein the conducting structure comprises a solder ball or a solder wire.
11. The method for forming a chip package as claimed in claim 10 , wherein the conducting structure is a solder ball, and the solder ball is located on a corner between the carrier substrate and the circuit board.
12. The method for forming a chip package as claimed in claim 8 , wherein the device region or sensing region is substantially and directly exposed.
13. A method for forming a chip package comprising:
providing a semiconductor substrate having an upper surface and a lower surface, wherein the semiconductor substrate comprises at least a device region or sensing region and at least a conducting pad on the upper surface of the semiconductor substrate;
providing a carrier substrate and disposing the semiconductor substrate overlying the carrier substrate;
forming a recess from the upper surface of the semiconductor substrate, wherein the recess extends into the carrier substrate;
forming an insulating layer overlying the upper surface of the semiconductor substrate and within the recess;
forming a conducting layer overlying the insulating layer, wherein the conducting layer is electrically connected to the conducting pad and extends from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and
dicing the carrier substrate from a bottom of the recess to form a plurality of separate chip packages.
14. The method for forming a chip package as claimed in claim 13 , further comprising:
providing a circuit board having a contact pad;
disposing the carrier substrate overlying the circuit board; and
forming a conducting structure, wherein the conducting structure is electrically connected to the contact pad and the conducting layer.
15. The method for forming a chip package as claimed in claim 14 , wherein the conducting structure comprises a solder ball or a solder wire.
16. The method for forming a chip package as claimed in claim 15 , wherein the conducting structure is a solder ball, and the solder ball is located on a corner between the carrier substrate and the circuit board.
17. The method for forming a chip package as claimed in claim 13 , wherein the device region or sensing region is substantially and directly exposed.