Semiconductor device with buried bit lines and method for fabricating the same
A semiconductor device includes active regions separated by a trench, a separation layer dividing the trench, and buried bit lines buried in the trench with the separation layer interposed between the buried bit lines.
1. A method for fabricating a semiconductor device, comprising:
etching a substrate and defining a trench which separates active regions;
forming a liner layer which has contact zones for exposing portions of sidewalls of the active regions; and
forming junctions on the exposed portions of the sidewalls of the active regions,
wherein the etching of a substrate and defining a trench which separates active regions includes defining at least three trenches each separating two active regions and wherein widths of two of the trenches is wider than the width of the remaining trench interposed between the two trenches.
2. The method of claim 1 , wherein the forming of the junctions comprises:
forming a dopant supply layer which gapfills the trench;
performing annealing of the dopant supply layer; and
removing the dopant supply layer.
3. The method of claim 2 , wherein the dopant supply layer comprises doped polysilicon.
4. The method of claim 1 , further comprising, after the forming of the junctions:
forming side contacts which are buried in the respective contact zones and are connected with the respective junctions; and
forming buried bit lines which are buried in the trench and are connected with the respective junctions through the respective side contacts.
5. The method of claim 1 , wherein the forming of the liner layer comprises:
forming a first liner layer which covers a surface of the trench;
forming a first sacrificial layer which gapfills the trench over the first liner layer;
recessing the first sacrificial layer and the first liner layer to a first depth and defining a first recess;
forming a second sacrificial layer which gapfills the first recess;
recessing the second sacrificial layer to a second depth and defining a second recess;
forming a second liner layer which covers surface portions of the active regions exposed by the second recess; and
removing a portion of the second liner layer, the second sacrificial layer and the first sacrificial layer.
6. The method of claim 5 , wherein the first liner layer and the second liner layer include nitride layers.
7. A method for fabricating a semiconductor device, comprising:
etching a substrate and defining a trench which separates active regions;
forming a separation layer which divides the trench into portions; and
forming buried bit lines which are each buried in the respective divided portion of the trench,
wherein the etching of a substrate and defining a trench which separates active regions includes defining at least three trenches each separating two active regions and wherein widths of two of the trenches is wider than the width of the remaining trench interposed between the two trenches.
8. The method of claim 7 , wherein the forming of the separation layer comprises:
forming a first dielectric layer which contacts sidewalls of the active regions;
forming a second dielectric layer which fills the trench; and
removing the first dielectric layer.
9. The method of claim 7 , wherein the first dielectric layer includes an oxide layer, and the second dielectric layer includes a nitride layer.
10. The method of claim 7 , wherein, before the forming of the buried bit lines, the method further comprises:
forming a liner layer having contact zones which expose portions of sidewalls of the active regions; and
forming junctions on exposed portions of the sidewalls of the active regions.
11. The method of claim 10 , wherein the method further comprises, after the forming of the junctions:
forming side contacts which are buried in the respective contact zones and are connected with the respective junctions.
12. The method of claim 11 , wherein the side contacts comprise a metal silicide layer.
13. A method for fabricating a semiconductor device, comprising:
etching a substrate and forming active regions which are separated by alternating ones of first trenches and second trenches, wherein the second trenches have a width smaller than that of the first trenches;
forming a junction on a sidewall of each of the active regions;
forming separation layers dividing the first trenches, respectively; and
forming buried bit lines which are buried in each of the first trenches with the respective separation layer interposed between the buried bit lines and are connected with the respective junctions.
14. The method of claim 13 , wherein the forming of the junction comprises:
forming a liner layer having contact zones which expose portions of sidewalls of the first trenches;
forming a dopant supply layer which gapfills the first trenches, on the liner layer;
performing annealing of the dopant supply layer; and
removing the dopant supply layer.
15. The method of claim 14 , wherein the dopant supply layer comprises doped polysilicon.