Memory devices having select gates with P type bodies, memory strings having separate source lines and methods
Memory devices and methods of operating memory devices are shown. Configurations described include a memory cell string having an elongated n type body region and having select gates with p type bodies. Configurations and methods shown can provide a reliable bias to a body region for memory operations such as erasing.
1. A memory device, comprising:
an elongated n type body region;
a p type source region coupled to a first end of the body region, and a p type drain region coupled to a second end of the body region;
a plurality of memory cell gates along a length of the elongated n type body region, each of the plurality of memory cell gates being separated from the elongated n type body region by at least a respective charge storage structure;
a drain select gate adjacent to the drain region, wherein the p type drain region comprises a body of the drain select gate; and
a source select gate adjacent to the source region, wherein the p type source region comprises a body of the source select gate.
2. The memory device of claim 1 , wherein the elongated n type body region is oriented vertically.
3. The memory device of claim 1 , wherein the elongated n type body region is oriented horizontally.
4. The memory device of claim 1 , wherein the elongated n type body region forms a “U” shape.
5. The memory device of claim 1 , further including a source line ohmically coupled to the source region.
6. The memory device of claim 1 , further including a source line and a p+ connecting region located between the source region and the source line.
7. The memory device of claim 1 , further including a source line directly coupled to the source region.
8. The memory device of claim 1 , further including a data line ohmicly coupled to the drain region.
9. The memory device of claim 1 , further including a data line, a plug directly coupled to the data line, and a p+ connecting region located between the drain region and the plug.
10. The memory device of claim 1 , further including a data line and a plug, the plug being directly coupled to the data line and directly coupled to the drain region.
11. A memory device, comprising:
an elongated n type body region;
a p type source region coupled to a first end of the body region, and a p type drain region coupled to a second end of the body region;
a plurality of memory cell gates along a length of the elongated n type body region, each of the plurality of memory cell gates being separated from the elongated n type body region by at least a respective charge storage structure;
a source line ohmicly coupled to the source region; and
a data line ohmicly coupled to the drain region.
12. The memory device of claim 11 , wherein the elongated n type body region comprises n− polysilicon.
13. The memory device of claim 12 , wherein the p type source region comprises p− polysilicon.
14. The memory device of claim 13 , wherein the p type drain region comprises p− polysilicon.
15. The memory device of claim 11 , wherein the source line comprises metal.
16. The memory device of claim 11 , wherein the source line comprises n+ polysilicon.
17. The memory device of claim 11 , further including a p+ region between the source line and the source region.
18. The memory device of claim 17 , further including a p+ region between the data line and the drain region.