Shift register and synchronization circuit using the same
A synchronization circuit includes a measurement unit configured to measure a difference between an initial delay amount of an input clock signal and an initial delay amount of a feedback clock signal and generate a phase difference detection signal, an initial delay time setting unit configured to generate an initial delay time setting signal in response to the phase difference detection signal, a shift register configured to generate a shift signal in response to the initial delay time setting signal, and a delay chain having an initial delay time set in response to the shift signal.
1. A synchronization circuit comprising:
a measurement unit configured to measure a difference between an initial delay amount of an input clock signal and an initial delay amount of a feedback clock signal and generate a phase difference detection signal;
an initial delay time setting unit configured to generate an initial delay time setting signal in response to the phase difference detection signal;
a shift register configured to generate a shift signal in response to the initial delay time setting signal; and
a delay chain having an initial delay time set in response to the shift signal.
2. The synchronization circuit according to claim 1 , wherein the measurement unit comprises:
a division section configured to divide the feedback clock signal and generate a divided clock signal; and
a phase difference detection section configured to detect a phase difference between the input clock signal and the divided clock signal and generate the phase difference detection signal.
3. The synchronization circuit according to claim 1 , wherein the initial delay time setting unit comprises:
an oscillator configured to perform an oscillation operation in response to the phase difference detection signal and generate the initial delay time setting signal.
4. The synchronization circuit according to claim 1 , wherein the initial delay time setting unit is configured to output oscillation signals, which are generated in a period corresponding to a pulse width of the phase difference detection signal at a predetermined time difference, as the initial delay time setting signal.
5. The synchronization circuit according to claim 4 , wherein the predetermined time difference is substantially identical to a unit delay time of the delay chain.
6. A synchronization circuit comprising:
a delay chain configured to delay and output an input clock signal;
a measurement unit configured to generate a phase difference detection signal and an initial delay time setting completion signal in response to the input clock signal and a feedback clock signal;
an initial delay time setting unit configured to generate a first control signal in response to the phase difference detection signal;
a control unit configured to generate a second control signal, which corresponds to a result obtained by comparing a phase of the input clock signal with a phase of the feedback clock signal, in response to activation of the initial delay time setting completion signal; and
a shift register configured to set an initial delay time of the delay chain in response to the first control signal and change a delay time of the delay chain in response to the second control signal.
7. The synchronization circuit according to claim 6 , wherein the measurement unit comprises:
a division section configured to divide the feedback clock signal and generate a divided clock signal;
a phase difference detection section configured to detect a phase difference between the input clock signal and the divided clock signal and generate the phase difference detection signal; and
an initial delay time setting completion signal generation section configured to generate the initial delay time setting completion signal in response to the phase difference detection signal and the divided clock signal.
8. The synchronization circuit according to claim 6 , wherein the initial delay time setting unit comprises:
an oscillator configured to perform an oscillation operation in response to the phase difference detection signal and generate the first control signal.
9. The synchronization circuit according to claim 6 , wherein the initial delay time setting unit is configured to output oscillation signals, which are generated in a period corresponding to a pulse width of the phase difference detection signal at a predetermined time difference, as the first control signal.
10. The synchronization circuit according to claim 9 , wherein the predetermined time difference is substantially identical to a unit delay time of the delay chain.
11. The synchronization circuit according to claim 6 , wherein the shift register is configured to shift its own output signal by one cipher in response to the second control signal and shift the output signal by two or more ciphers in response to the first control signal.
12. A synchronization circuit comprising:
a measurement unit configured to generate a phase difference detection signal and an initial delay time setting completion signal in response to an input clock signal and a feedback clock signal;
an initial delay time setting unit configured to generate a first control signal in response to the phase difference detection signal;
a control unit configured to generate a second control signal or a third control signal, which corresponds to a result obtained by comparing a phase of the input clock signal with a phase of the feedback clock signal, in response to activation of the initial delay time setting completion signal;
a first delay chain configured to delay and output the input clock signal; a second delay chain configured to delay and output an output signal of the first delay chain in response to the third control signal; and
a shift register configured to set an initial delay time of the first delay chain in response to the first control signal and change a delay time of the first delay chain in response to the second control signal.
13. The synchronization circuit according to claim 12 , wherein the measurement unit comprises:
a division section configured to divide the feedback clock signal and generate a divided clock signal;
a phase difference detection section configured to detect a phase difference between the input clock signal and the divided clock signal and generate the phase difference detection signal; and
an initial delay time setting completion signal generation section configured to generate the initial delay time setting completion signal in response to the phase difference detection signal and the divided clock signal.
14. The synchronization circuit according to claim 12 , wherein the initial delay time setting unit comprises:
an oscillator configured to perform an oscillation operation in response to the phase difference detection signal and generate the first control signal.
15. The synchronization circuit according to claim 12 , wherein the initial delay time setting unit is configured to output oscillation signals, which are generated in a period corresponding to a pulse width of the phase difference detection signal at a predetermined time difference, as the first control signal.
16. The synchronization circuit according to claim 15 , wherein the predetermined time difference is substantially identical to a unit delay time of the delay chain.
17. The synchronization circuit according to claim 12 , wherein the shift register is configured to shift its own output signal by one cipher in response to the second control signal and shift the output signal by two or more ciphers in response to the first control signal.