IP Library Granted Patent US 8,546,180
Granted Patent B2
US 8,546,180 · App. 12/846,534 · Granted Oct 1, 2013

Method for manufacturing oxide semiconductor device

Inventors: Shunpei Yamazaki (Tokyo, JP); Hiroki Ohara (Kanagawa, JP); Toshinari Sasaki (Kanagawa, JP); Kosei Noda (Kanagawa, JP); Hideaki Kuwabara (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
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Quick Facts
Patent No.
US 8,546,180
App. No.
12/846,534
Granted
Oct 1, 2013
Kind
B2
Abstract

An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.

Claims (57)

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode layer over an insulating surface;

forming a gate insulating layer over the gate electrode layer;

forming an oxide semiconductor layer over the gate insulating layer;

dehydrating or dehydrogenating the oxide semiconductor layer;

forming an oxide insulating layer which is in contact with part of the oxide semiconductor layer and covering a periphery and a side surface of the oxide semiconductor layer;

forming a source electrode layer and a drain electrode layer over the oxide insulating layer; and

forming a protective insulating layer which is in contact with the oxide insulating layer, the source electrode layer, the drain electrode layer, and the oxide semiconductor layer,

wherein the oxide semiconductor layer is prevented from being exposed to air between the step of dehydrating or dehydrogenating the oxide semiconductor layer and the step of forming the oxide insulating layer, so as to prevent water or hydrogen contamination.

2. The method for manufacturing a semiconductor device, according to claim 1 , wherein the oxide insulating layer is formed using a silicon oxide film or an aluminum oxide film which is formed by a sputtering method.

3. The method for manufacturing a semiconductor device, according to claim 1 , wherein the protective insulating layer is formed using a silicon nitride film or an aluminum nitride film which is formed by a sputtering method.

4. The method for manufacturing a semiconductor device, according to claim 1 , further comprising:

forming a conductive layer over the protective insulating layer, and

wherein the conductive layer overlaps the gate electrode layer,

wherein the conductive layer overlaps a part of the oxide semiconductor layer which is in contact with the protective insulating layer.

5. The method for manufacturing a semiconductor device, according to claim 1 , wherein the gate electrode layer is formed using a transparent conductive film, and wherein the source electrode layer and the drain electrode layer are formed using a metal conductive film.

6. The method for manufacturing a semiconductor device, according to claim 1 , wherein a width in a channel length direction of the gate electrode layer is larger than a width in a channel length direction of the oxide semiconductor layer, and

wherein an end surface of the gate electrode layer overlaps with the source electrode layer or the drain electrode layer with the gate insulating layer and the oxide insulating layer interposed therebetween.

7. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first gate electrode layer over an insulating surface;

forming a second gate electrode layer over the insulating surface;

forming a gate insulating layer over the first and second gate electrode layers;

forming a first oxide semiconductor layer and a second oxide semiconductor layer over the gate insulating layer;

dehydrating or dehydrogenating the first and second oxide semiconductor layers;

forming an oxide insulating layer which is in contact with part of the first and second oxide semiconductor layers and covering a periphery and a side surface of the first and second oxide semiconductor layers;

forming a first source electrode layer and a first drain electrode layer over the first oxide insulating layer;

forming a second source electrode layer and a second drain electrode layer over the second oxide insulating layer; and

forming a protective insulating layer which is in contact with the oxide insulating layer, the first source electrode layer, the first drain electrode layer, and the first oxide semiconductor layer,

wherein the first and second oxide semiconductor layers are prevented from being exposed to air between the step of dehydrating or dehydrogenating the first and second oxide semiconductor layers and the step of forming the oxide insulating layer, so as to prevent water or hydrogen contamination.

8. The method for manufacturing a semiconductor device, according to claim 7 , wherein the second gate electrode layer and the second source electrode layer and the second drain electrode layer are formed using a transparent conductive film which is formed by a sputtering method.

9. The method for manufacturing a semiconductor device, according to claim 7 , wherein the first and second gate electrode layers and the second source electrode layer and the second drain electrode layer are formed using a transparent conductive film which is formed by a sputtering method.

10. The method for manufacturing a semiconductor device, according to claim 7 , wherein the first gate electrode layer and the first source electrode layer and the first drain electrode layer are formed using a metal conductive film which is formed by a sputtering method.

11. The method for manufacturing a semiconductor device, according to claim 7 , wherein a width in a channel length direction of the first gate electrode layer is larger than a width in a channel length direction of the first oxide semiconductor layer, and

wherein an end surface of the gate first electrode layer overlaps with the first source electrode layer or the first drain electrode layer with the first gate insulating layer and the first oxide insulating layer interposed therebetween.

12. The method for manufacturing a semiconductor device, according to claim 7 , wherein a width in a channel length direction of the first gate electrode layer is larger than a width in a channel length direction of the first oxide semiconductor layer, and

wherein a width in a channel length direction of the second gate electrode layer is smaller than a width in a channel length direction of the second oxide semiconductor layer.

13. The method for manufacturing a semiconductor device, according to claim 7 , wherein the oxide insulating layer has openings,

wherein one of the openings overlaps with the second semiconductor layer,

wherein the one of the openings is covered with the second source electrode layer or the second drain electrode layer.

14. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode layer over an insulating surface;

forming a gate insulating layer over the gate electrode layer;

forming an oxide semiconductor layer over the gate insulating layer;

dehydrating or dehydrogenating the oxide semiconductor layer;

forming an oxide insulating layer which is in contact with an upper surface of the oxide semiconductor layer and covering a periphery and a side surface of the oxide semiconductor layer;

after forming the oxide semiconductor layer, forming a source electrode layer and a drain electrode layer on and in contact with the oxide insulating layer; and

after forming the source electrode layer and the drain electrode layer, forming a protective insulating layer which is in contact with the oxide insulating layer, the source electrode layer, and the drain electrode layer,

wherein the oxide semiconductor layer is prevented from being exposed to air between the step of dehydrating or dehydrogenating the oxide semiconductor layer and the step of forming the oxide insulating layer, so as to prevent water or hydrogen contamination.

15. The method for manufacturing a semiconductor device, according to claim 14 , wherein the oxide insulating layer is formed using a silicon oxide film or an aluminum oxide film which is formed by a sputtering method.

16. The method for manufacturing a semiconductor device, according to claim 14 , wherein the protective insulating layer is formed using a silicon nitride film or an aluminum nitride film which is formed by a sputtering method.

17. The method for manufacturing a semiconductor device, according to claim 14 , further comprising:

forming a conductive layer over the protective insulating layer,

wherein the conductive layer overlaps the gate electrode layer, and

wherein the conductive layer overlaps a part of the oxide semiconductor layer which is in contact with the protective insulating layer.

18. The method for manufacturing a semiconductor device, according to claim 14 , wherein the gate electrode layer is formed using a transparent conductive film, and wherein the source electrode layer and the drain electrode layer are formed using a metal conductive film.

19. The method for manufacturing a semiconductor device, according to claim 14 , wherein a width in a channel length direction of the gate electrode layer is larger than a width in a channel length direction of the oxide semiconductor layer, and

wherein an end surface of the gate electrode layer overlaps with the source electrode layer or the drain electrode layer with the gate insulating layer and the oxide insulating layer interposed therebetween.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2010
From: YAMAZAKI, SHUNPEI; OHARA, HIROKI; SASAKI, TOSHINARI; NODA, KOSEI; KUWABARA, HIDEAKI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 024796/0246 →
Priority Claims (1)
JP 2009-179773 · Jul 31, 2009 · national
Continuity (1)
Related Publication 20110024750A1 · Feb 3, 2011