Add instructions to add three source operands
A method in one aspect may include receiving an add instruction. The add instruction may indicate a first source operand, a second source operand, and a third source operand. A sum of the first, second, and third source operands may be stored as a result of the add instruction. The sum may be stored partly in a destination operand indicated by the add instruction and partly a plurality of flags. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.
1. A method comprising:
receiving an add instruction, the add instruction indicating a first source operand, a second source operand, and a third source operand; and
storing a sum calculated using the first, second, and third source operands as a result of the add instruction, in which the sum is stored partly in a destination operand indicated by the add instruction and partly in a plurality of flags.
2. The method of claim 1 , wherein storing comprises storing a next to most significant bit of the sum in a first flag of the plurality and a most significant bit of the sum in a second flag of the plurality.
3. The method of claim 1 , wherein storing the sum partly in the flags comprises storing the sum partly in a carry flag and partly in a second flag.
4. The method of claim 3 , wherein the second flag comprises a re-purposed architectural flag.
5. The method of claim 3 , wherein the second flag comprises an overflow flag.
6. The method of claim 1 , wherein storing the sum comprises storing a sum of the first, second, and third source operands added to a combination of the plurality of flags.
7. The method of claim 6 , wherein storing the sum comprises storing a sum of the first, second, and third source operands added to a first flag of the plurality and added to a product that is two times a second flag of the plurality.
8. The method of claim 6 , wherein the combination of the plurality of flags includes an overflow flag, and wherein the source operands comprise unsigned integers.
9. The method of claim 1 , wherein receiving comprises receiving an add instruction that implicitly indicates a source operand selected from the first, second, and third source operands as a register that is implicitly indicated as a destination operand of an integer multiply instruction of same instruction set architecture.
10. The method of claim 1 , wherein the first, second, and third source operands are unsigned integer operands having a size selected from 32-bits and 64-bits.
11. The method of claim 1 , performed as part of a multiplication of large integers that are larger than a size of registers used to store them.
12. The method of claim 1 , wherein the method is performed by a general-purpose microprocessor having a plurality of cores, and wherein at least one of the cores has circuitry responsive to the instruction.
13. An apparatus comprising:
an execution unit that is operable as a result of an add instruction indicating a first source operand, a second source operand, and a third source operand, to store a sum calculated using the first, second, and third source operands, in which the sum is stored partly in a destination operand indicated by the add instruction and partly in a plurality of flags.
14. The apparatus of claim 13 , wherein the execution unit is operable to store a next to most significant bit of the sum in a first flag of the plurality and a most significant bit of the sum in a second flag of the plurality.
15. The apparatus of claim 13 , wherein the execution unit is operable to store the sum partly in a carry flag and partly in a second flag.
16. The apparatus of claim 15 , wherein the second flag comprises a re-purposed architectural flag.
17. The apparatus of claim 15 , wherein the second flag comprises an overflow flag.
18. The apparatus of claim 13 , wherein the execution unit is operable to store a sum of the first, second, and third source operands added to a combination of the plurality of flags.
19. The apparatus of claim 18 , wherein the execution unit is operable to store a sum of the first, second, and third source operands added to a first flag of the plurality and added to a product that is two times a second flag of the plurality.
20. The apparatus of claim 18 , wherein the execution unit is operable to store a sum of the first, second, and third source operands added to a combination of flags that includes an overflow flag, and wherein the source operands comprise unsigned integers.
21. The apparatus of claim 13 , wherein the execution unit is responsive to an add instruction that implicitly indicates a source operand selected from the first, second, and third source operands as a register that is implicitly indicated as a destination operand of an integer multiply instruction of a same instruction set architecture.
22. The apparatus of claim 13 , wherein the execution unit is responsive to an add instruction that specifies the source operands which have unsigned integers having a size selected from 32-bits and 64-bits.
23. The apparatus of claim 13 , wherein the execution unit is included within a core of a multi-core general-purpose microprocessor.
24. The apparatus of claim 13 , wherein the execution unit is included within a special-purpose cryptographic device.
25. An apparatus comprising:
an execution unit that is operable as a result of an add instruction indicating a first source operand, a second source operand, and a third source operand each having unsigned integers, to store a sum calculated using the first, second, and third source operands added to a combination of a plurality of flags, in which the sum is stored partly in a destination operand indicated by the add instruction and partly in the plurality of flags.
26. The apparatus of claim 25 , wherein the execution unit is operable to store a sum of the first, second, and third source operands added to a first flag of the plurality and added to a product that is two times a second flag of the plurality.
27. A system comprising:
an interconnect;
a processor coupled with the interconnect, the processor operable as a result of an add instruction indicating a first source operand, a second source operand, and a third source operand, to store a sum calculated using the first, second, and third source operands, in which the sum is stored partly in a destination operand indicated by the add instruction and partly in a plurality of flags; and
a dynamic random access memory (DRAM) coupled with the interconnect.
28. The system of claim 27 , wherein the processor is operable to store a sum of the first, second, and third source operands added to a combination of the plurality of flags.
29. An article of manufacture comprising:
a non-transitory machine-readable storage medium including solid matter to store an add instruction,
the add instruction to indicate a first source operand, a second source operand, and a third source operand and if executed by a machine to cause the machine to perform operations comprising:
calculating a sum using the first, second, and third source operands; and
storing the sum partly in a destination operand indicated by the add instruction and partly in a plurality of flags.
30. The article of claim 29 , wherein the processor is operable to calculate the sum of the first, second, and third source operands added to a combination of the plurality of flags.