IP Library › Granted Patent US 8,551,840
Granted Patent B2
US 8,551,840 · App. 13/069,636 · Granted Oct 8, 2013

Methods of forming phase-change memory devices and devices so formed

Inventor: Youngnam Hwang (Hwaseong-si, KR)
Assignee: Samsung Electronics Co., Ltd.
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Quick Facts
Patent No.
US 8,551,840
App. No.
13/069,636
Granted
Oct 8, 2013
Kind
B2
Abstract

A method of forming can be provided by forming a metal silicide layer that includes a diffusion metal on a substrate. A native oxide layer can be formed on the metal silicide layer and forming a metal oxide layer by reacting the native oxide layer with the diffusion metal. A phase-change layer and an upper electrode can be formed on the metal oxide layer. A phase-change memory device can include a substrate and a conductive region on the substrate with a lower electrode on the conductive region, where the lower electrode can include a metal silicide layer on the conductive region and a metal silicon nitride layer having a resistivity of about 10 to about 100 times that of the metal silicide layer. A metal oxide layer can be located between the metal silicon nitride layer and the metal silicide layer, the metal oxide layer comprising a resistivity that is greater than that of the metal silicide layer and less than the resistivity of the metal silicon nitride layer. A phase-change layer and an upper electrode can be located on the lower electrode.

Claims (35)

1. A method of forming comprising:

forming a metal silicide layer including a diffusion metal on a substrate;

forming a native oxide layer on the metal silicide layer;

forming a metal oxide layer on the metal silicide layer by reacting the native oxide layer with the diffusion metal; and

forming a phase-change layer and an upper electrode on the metal oxide layer, wherein forming the metal silicide layer comprises:

forming a first metal layer containing a silicide reactive metal and a second metal layer containing the diffusion metal on the substrate; and

performing a first annealing on the first metal layer and the second metal layer before forming the native oxide layer.

2. The method of claim 1 , wherein the silicide reactive metal comprises at least one of cobalt and nickel.

3. The method of claim 1 , wherein forming the metal silicide layer further comprises:

removing the first metal layer and the second metal layer remaining on the metal silicide layer.

4. The method of claim 1 , wherein forming the metal silicide layer further comprises:

forming a protective metal layer on the first metal layer and the second metal layer.

5. The method of claim 1 , wherein the diffusion metal comprises at least one of titanium, tantalum, tungsten, molybdenum, vanadium, hafnium and zirconium.

6. The method of claim 5 , wherein forming the metal oxide layer comprises performing a second annealing on the native oxide layer to replace an insulating constituent of the native oxide layer with the diffusion metal.

7. The method of claim 6 , wherein the metal oxide layer comprises at least one of a titanium oxide layer, a tantalum oxide layer, a tungsten oxide layer, a molybdenum oxide layer, a vanadium oxide layer, a hafnium oxide layer and a zirconium oxide layer.

8. The method of claim 6 , wherein forming the metal oxide layer further comprises:

forming a resistive metal layer on the substrate before or after the second annealing.

9. The method of claim 8 , wherein the resistive metal layer comprises a metal silicon nitride layer.

10. The method of claim 9 , wherein the metal silicon nitride layer is formed by metal-organic chemical vapor deposition.

11. The method of claim 9 , wherein the metal silicon nitride layer comprises at least one of a titanium silicon nitride layer, a tantalum silicon nitride layer, a zirconium silicon nitride layer and a tungsten silicon nitride layer.

12. A method of forming a phase-change memory device, the method comprising:

forming a diode on a substrate including an upper conductive layer;

forming a first metal layer including a diffusion metal on the upper conductive layer;

forming a metal silicide layer on the upper conductive layer including the diffusion metal;

forming a metal oxide layer from and on the metal silicide layer;

forming a metal silicon nitride layer on the metal oxide layer; and

forming a phase-change layer and an upper electrode on the metal silicon nitride layer that is on the metal oxide layer.

13. The method of claim 12 , further comprising:

forming a second metal layer above the first metal layer, the second metal layer comprising a metal constituent included in the metal silicide layer.

14. The method of claim 12 , further comprising:

forming a second metal layer beneath the first metal layer, the second metal layer comprising a metal constituent included in the metal silicide layer.

15. The method of claim 13 , wherein forming a metal oxide layer comprises forming a native oxide layer on the metal silicide layer; and

replacing an oxide constituent in the native oxide layer with the diffusion metal.

16. The method of claim 1 , wherein a melting point of the diffusion metal is different from that of the metal silicide layer.

17. The method of claim 12 , wherein a melting point of the diffusion metal is different from that of the metal silicide layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 23, 2011
From: HWANG, YOUNGNAM
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 026004/0527 →
Priority Claims (1)
KR 10-2010-0025910 · Mar 23, 2010 · national
Continuity (1)
Related Publication 20110233503A1 · Sep 29, 2011