Integrated circuit devices including vertical channel transistors with shield lines interposed between bit lines and methods of fabricating the same
An integrated circuit device includes a plurality of pillars protruding from a substrate in a first direction. Each of the pillars includes source/drain regions in opposite ends thereof and a channel region extending between the source/drain regions. A plurality of conductive bit lines extends on the substrate adjacent the pillars in a second direction substantially perpendicular to the first direction. A plurality of conductive shield lines extends on the substrate in the second direction such that each of the shield lines extends between adjacent ones of the bit lines. Related fabrication methods are also discussed.
1. An integrated circuit device, comprising:
a plurality of pillars protruding from a substrate in a first direction, each of the pillars including source/drain regions in opposite ends thereof and a channel region extending between the source/drain regions;
a plurality of conductive bit lines on the substrate adjacent the pillars and extending in a second direction substantially perpendicular to the first direction; and
a plurality of conductive shield lines on the substrate and extending in the second direction, each of the shield lines extending between adjacent ones of the bit lines,
wherein the shield lines extend towards the substrate in a direction opposite the first direction beyond the bit lines.
2. The device of claim 1 , wherein each of the bit lines electrically contacts a respective one of the source/drain regions of a respective one of the pillars adjacent thereto, and wherein each of the shield lines is electrically insulated from the respective one of the source/drain regions.
3. The device of claim 2 , further comprising:
respective shield insulating layers between sidewalls of the shield lines and sidewalls of ones of the bit lines adjacent thereto,
wherein each of the shield lines is electrically insulated from the ones of the bit lines adjacent thereto by the respective shield insulating layers.
4. The device of claim 2 , further comprising:
respective air gaps between sidewalls of the shield lines and sidewalls of ones of the bit lines adjacent thereto,
wherein each of the shield lines is electrically insulated from the ones of the bit lines adjacent thereto by the respective air gaps.
5. The device of claim 2 , wherein the shield lines do not provide electrical interconnections for the device.
6. The device of claim 2 , wherein each of the bit lines extends on the substrate in the second direction adjacent a base of the respective one of the pillars adjacent thereto.
7. The device of claim 1 , further comprising:
a plurality of conductive word lines extending in a third direction substantially perpendicular to the first and second directions, wherein each of the word lines extends on ones of the pillars between the source/drain regions thereof.
8. The device of claim 7 , wherein the word lines are spaced apart from each other along the second direction, and wherein the bit lines are spaced apart from each other along the third direction.
9. The device of claim 1 , wherein the shield lines are directly on the substrate.
10. The device of claim 9 , wherein the substrate comprises silicon, and wherein the shield lines comprise epitaxial layers of doped silicon.
11. The device of claim 9 , wherein each of the shield lines is provided in a respective trench in the substrate that extends between sidewalls of the adjacent ones of the bit lines.
12. An integrated circuit device, comprising:
a plurality of pillars protruding from a substrate in a first direction, each of the pillars including source/drain regions in opposite ends thereof and a channel region extending between the source/drain regions;
a plurality of conductive bit lines on the substrate adjacent the pillars and extending in a second direction substantially perpendicular to the first direction;
a plurality of conductive shield lines directly on the substrate and extending in the second direction, each of the shield lines extending between adjacent ones of the bit lines; and
a junction oxide layer between the plurality of pillars and the substrate, the junction oxide layer including the plurality of bit lines thereon,
wherein each of the shield lines is provided in a respective trench in the junction oxide layer between sidewalls of the adjacent ones of the bit lines.
13. The device of claim 1 , wherein the shield lines further extend away from the substrate in the first direction to a substantially similar level as the bit lines.
14. The device of claim 1 , wherein the shield lines further extend away from the substrate in the first direction beyond the bit lines.
15. An integrated circuit device, comprising:
a plurality of pillars protruding from a substrate in a first direction, each of the pillars including source/drain regions in opposite ends thereof and a channel region extending between the source/drain regions;
a plurality of conductive bit lines on the substrate adjacent the pillars and extending in a second direction substantially perpendicular to the first direction; and
a plurality of conductive shield lines on the substrate and extending in the second direction, each of the shield lines extending between adjacent ones of the bit lines
wherein the shield lines comprise first and second shield lines, wherein each of the first shield lines includes shield insulating layers directly on sidewalls of the adjacent ones of the bit lines, and wherein each of the second shield lines is separated from the sidewalls of the adjacent ones of the bit lines by ones of the pillars adjacent thereto.
16. The device of claim 15 , wherein the first and second shield lines comprise a same material.
17. The device of claim 1 , wherein the shield lines and the bit lines comprise a same material.
18. The device of claim 1 , wherein the bit lines and/or the shield lines comprise a metal including tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), tantalum (Ta), or ruthenium (Ru), and/or a metal nitride including TiN, TiN/W, Ti/TiN, WN, W/WN, TaN, Ta/TaN, TiSiN, TaSiN, or WSiN.