Isolation method and package using a high isolation differential ball grid array (BGA) pattern
According to an embodiment an improved Application Specific Integrated Circuit (ASIC) isolation method and system for assigning signal pins in an ASIC package having a plurality of signal pins is disclosed. The method and system comprise identifying an isolation requirement of the ASIC and determining an optimized pattern for substantially diagonal pairing of signal pins in relation to the isolation requirement. The method includes pairing signal pairs substantially diagonally in accordance with the pattern.
1. A computer based method to arrange signal pins for pairing in an integrated circuit, comprising:
determining, in a computer system, an isolation requirement and an area for the integrated circuit;
determining, in the computer system, a signal pin pattern that satisfies the isolation requirement within the area by repetitively performing operations, comprising:
determining, in the computer system, available signal and ground pin pairs within the area for the integrated circuit;
identifying, in the computer system, two diagonally adjacent signal pins;
assigning, in the computer system, the two diagonally adjacent signal pins as a first diagonally adjacent signal pin pair;
identifying, in the computer system, a diagonal reference line which extends perpendicularly from the first signal pin pair;
identifying, in the computer system, a closest pair of signal pins which reside on the diagonal reference line; and
adding, in the computer system, the closest pair of signal pins to the layout.
2. The computer based method of claim 1 , further comprising determining, in the computer system, a maximal area of the integrated circuit.
3. The computer based method of claim 1 , further comprising:
identifying, in the computer system, signal pins proximate the first adjacent signal pin pair which do not lie on the diagonal reference line; and
moving, in the computer system, the signal pins away from the first adjacent signal pin pair.
4. The computer based method of claim 3 , further comprising:
replacing, in the computer system, the signal pins moved away from the first adjacent with a ground pin or a power pin.
5. The computer based method of claim 4 , further comprising generating, in the computer system, the layout pattern.
6. The computer based method of claim 5 , wherein the layout pattern is generated in relation to a limitation with respect to the integrated circuit footprint.
7. The computer based method of claim 6 , wherein the layout pattern is generated for an integrated circuit which is within a Ball Grid Array (BGA).
8. A computer based method to determine an integrated circuit signal pin layout by performing operations, comprising:
(a) determining, in a computer system, available signal and ground pin pairs within the area for the integrated circuit;
(b) identifying, in the computer system, two diagonally adjacent signal pins;
(c) assigning, in the computer system, the two diagonally adjacent signal pins as a diagonally adjacent signal pin pair;
(d) identifying, in the computer system, a diagonal reference line which extends perpendicularly from the diagonally adjacent signal pin pair;
(e) identifying, in the computer system, a closest pair of signal pins which reside on the diagonal reference line;
(f) adding, in the computer system, the closest pair of signal pins to the layout;
(g) identifying, in the computer system, signal pins proximate the first diagonally adjacent signal pin pair which do not lie on the diagonal reference line; and
(h) moving, in the computer system, the signal pins away from the first adjacent signal pin pair.
9. The computer based method of claim 1 , further comprising:
determining, in the computer system, an isolation requirement and a maximal area of the integrated circuit.
10. The computer based method of claim 9 , further comprising:
repeating, in the computer system, operations (a) through (f) until a signal pin layout is generated which satisfies the isolation requirement within the maximal area of the integrated circuit.
11. The computer based method of claim 10 , further comprising generating, in the computer system, the layout pattern.
12. The computer based method of claim 11 , wherein the layout pattern is generated for an ASIC which is within a Ball Grid Array (BGA).
13. A computer-based system to generate an integrated circuit signal pin layout by implementing operations, comprising:
(a) determining, in the computer system, available signal and ground pin pairs within the area for the integrated circuit;
(b) identifying, in the computer system, two diagonally adjacent signal pins;
(c) assigning, in the computer system, the two diagonally adjacent signal pins as a diagonally adjacent signal pin pair;
(d) identifying, in the computer system, a diagonal reference line which extends perpendicularly from the diagonally adjacent signal pin pair;
(e) identifying, in the computer system, a closest pair of signal pins which reside on the diagonal reference line;
(f) adding, in the computer system, the closest pair of signal pins to the layout;
(g) identifying, in the computer system, signal pins proximate the first diagonally adjacent signal pin pair which do not lie on the diagonal reference line; and
(h) moving, in the computer system, the signal pins away from the first adjacent signal pin pair.
14. The computer-based system of claim 13 , further comprising:
determining and isolation requirement and a maximal area of the integrated circuit.
15. The computer-based system of claim 13 , wherein the computer system repeats operations (a) through (f) until a signal pin layout is generated which satisfies the isolation requirement within the maximal area of the integrated circuit.
16. The computer-based system of claim 14 wherein the computer system generates the layout pattern.
17. The computer-based system of claim 14 , wherein the layout pattern is generated for an ASIC which is within a Ball Grid Array (BGA).