Multilayer ceramic capacitor
There is provided a multilayer ceramic capacitor. The capacitor includes: a multilayer body having a dielectric layer; and first and second internal electrodes disposed in the multilayer body, the dielectric layer being disposed between the first and second internal electrodes, wherein, in a cross-section taken in a width-thickness direction of the multilayer body, an offset portion is defined as a portion where adjacent first and second internal electrodes do not overlap with each other, and a ratio (t 1 /td) of a width t 1 of the offset portion to a thickness td of the dielectric layer is 1 to 10.
1. A multilayer ceramic capacitor having a length and a width of 0.6±0.09 mm and 0.3±0.09 mm, respectively, comprising:
a multilayer body having a dielectric layer; and
first internal electrodes and second internal electrodes disposed in the multilayer body, the dielectric layer being disposed between each of the first and second internal electrodes;
wherein, in a cross-section taken in a width-thickness direction of the multilayer body, the first and second internal electrodes are offset in a width direction, and an offset portion is defined as a portion where adjacent first and second internal electrodes do not overlap with each other, the second internal electrodes are alternately offset to the right and left, in the width direction with respect to the first internal electrodes, and
wherein a ratio (t 1 /td) of a width t 1 of the offset portion to a thickness td of the dielectric layer is satisfies 1≦t 1 /td≦10,
the width t 1 is defined as a minimum width of the offset portion, and the thickness td of the dielectric layer is defined as an average thickness of the dielectric layers, and
the thickness td of the dielectric layer is 0.65 μm or less.
2. The multilayer ceramic capacitor of claim 1 , wherein the width t 1 ranges from 0.8 μm to 5.8 μm.
3. The multilayer capacitor of claim 1 , wherein 200 or more dielectric layers are laminated.
4. The multilayer ceramic capacitor of claim 1 , wherein the thickness td of the dielectric layer ranges from 0.55 μm to 0.65 μm.
5. A multilayer ceramic capacitor having a length and width of 0.6±0.09 mm and 0.3±0.09 mm, respectively, comprising:
a multilayer body having first and second sides;
first internal electrodes and second internal electrodes provided in the multilayer body, and having ends exposed to the first and second sides, respectively; and
a dielectric layer disposed between each of the first and second internal electrodes and having a thickness td of 0.65 μm or less,
wherein, in a width-thickness cross-section of the multilayer body, a ratio (t 1 /td) of a minimum width t 1 of an offset portion to the thickness td of the dielectric layer satisfies 1≦t 1 /td≦10,
wherein the offset portion is defined as a portion where adjacent first and second internal electrodes do not overlap to be offset from each other, and the second internal electrodes are alternately offset to the right and left, in the width direction with respect to the first internal electrodes.
6. The multilayer ceramic capacitor of claim 5 , wherein them thickness td of the dielectric layer is a distance between the first and second internal electrodes disposed to be adjacent.
7. The capacitor of claim 5 , wherein the minimum width t 1 ranges from 0.8 μm to 5.8 μm.
8. The multilayer ceramic capacitor of claim 5 , wherein 200 or more dielectric layers are laminated.
9. The multilayer ceramic capacitor of claim 5 , wherein the thickness td of the dielectric layer ranges from 0.55 μm to 0.65 μm.
10. A multilayer ceramic capacitor having a length and width of 0.6±0.09 mm and 0.3±0.09 mm, respectively, comprising:
a multilayer body having first and second sides;
first internal electrodes and second internal electrodes provided in the multilayer body, and having ends exposed to the first and second sides, respectively,
wherein, in a cross-section of the multilayer body, substantially perpendicular to a first direction thereof, a ratio (t 1 /td) of a width t 1 of an offset portion where the first and second internal electrodes disposed to be adjacently offset from each other in a second direction substantially perpendicular to the first direction, to a distance td between the first and second internal electrodes disposed to be adjacent satisfies 1≦t 1 /td≦10,
the distance td between the first and second internal electrodes disposed to be adjacent is 0.65 μm or less,
the width t 1 is defined as a minimum width of the offset portion, and
the second internal electrodes are alternately offset to the right and left, in the width direction with respect to the first internal electrodes.
11. The capacitor of claim 10 , wherein the width t 1 of the offset portion ranges from 0.8 μm to 5.8 μm.
12. The multilayer ceramic capacitor of claim 10 , wherein 200 or more dielectric layers are a laminated.
13. The multilayer ceramic capacitor of claim 10 , wherein the distance td between the first and second internal electrodes disposed to be adjacent ranges from 0.55 μm to 0.65 μm.