Device and method for reducing impedance
A printed wiring board semiconductor package or PWB power core comprising singulated capacitors embedded on multiple layers of the printed wiring board semiconductor package wherein at least a part of each embedded capacitor lies within the die shadow and wherein the embedded, singulated capacitors comprise at least a first electrode and a second electrode. The first electrodes and second electrodes of the embedded singulated capacitors are interconnected to the Vcc (power) terminals and the Vss (ground) terminals respectively of a semiconductor device. The size of the embedded capacitors are varied to produce different self-resonant frequencies and their vertical placements within the PWB semiconductor package are used to control the inherent inductance of the capacitor-semiconductor electrical interconnections so that customized resonant frequencies of the embedded capacitors can be achieved with low impedance.
1. A method of making a printed wiring board semiconductor package, the method comprising,
providing a first inner layer panel including a first inner layer panel capacitor;
providing a second inner layer panel including a second inner layer panel capacitor, wherein the first inner layer panel capacitor comprises an area that differs from that of the second inner layer panel capacitor;
laminating the first and second inner layer panels together in overlying succession such that the first and second inner layer capacitors are at differing vertical positions within the printed wiring board semiconductor package, wherein the first inner layer panel is stacked on and adjacent to the second inner layer panel;
providing a semiconductor that projects a die shadow onto the printed wiring board semiconductor package, wherein at least a part of each of the first and second inner layer panel capacitors lies within the die shadow; and
interconnecting the first and second inner layer capacitors to a semiconductor through a conductive via.
2. The method of claim 1 , wherein said interconnecting the first and second inner layer capacitors to the semiconductor comprises interconnecting the first and second inner layer capacitors using a conductive trace on a same plane.
3. The method of claim 1 , wherein said interconnecting the first and second inner layer capacitors to the semiconductor comprises interconnecting the first and second inner layer capacitors using a conductive via connection selected from the group consisting of a micro via and a through via.
4. The method of claim 1 , wherein the conductive via connection is achieved by mechanical means or by laser means.
5. A method of making a printed wiring board semiconductor package, the method comprising:
creating a printed wiring board semiconductor package, wherein said creating a printed wiring board semiconductor package includes:
providing a first inner layer panel including a first inner layer panel capacitor;
providing a second inner layer panel including a second inner layer panel capacitor, wherein the first inner layer panel capacitor comprises an area that differs from that of the second inner layer panel capacitor;
laminating the first and second inner layer panels together in overlying succession such that the first and second inner layer capacitors are at differing vertical positions-within the printed wiring board semiconductor package, wherein the first inner layer panel is stacked on and adjacent to the second inner layer panel; and
interconnecting the first and second inner layer capacitors to a semiconductor through a conductive via; and
attaching to the printed wiring board semiconductor package a semiconductor which projects a die shadow onto the printed wiring board semiconductor package.
6. The method of claim 5 , wherein the interconnecting the first and second inner layer capacitors to the semiconductor through a conductive via comprises interconnecting the first and second inner layer capacitors to the semiconductor through a conductive via connection selected from the group consisting of a micro via and a through via.
7. The method of claim 5 , further comprising interconnecting the first and second inner layer capacitors to each other through a conductive trace in the same plane or through a conductive via connection selected from the group consisting of a micro via and a through via.
8. The method of claim 6 , wherein the conductive via connection is achieved by mechanical means or by laser means.
9. A printed wiring board semiconductor package comprising:
a first inner layer panel including a first inner layer panel capacitor; and
a second inner layer panel including a second inner layer panel capacitor, wherein the first inner layer panel is stacked on and adjacent to the second inner layer panel; and wherein the first and second inner layer panels are laminated together in overlying succession such that the first and second inner layer panel capacitors are at differing vertical positions within the printed wiring board semiconductor package;
a semiconductor that projects a die shadow onto the printed wiring board semiconductor package, wherein at least a part of each of the first and second inner layer panel capacitors lies within the die shadow; and
a conductive via interconnecting the first and second inner layer capacitors to the semiconductor.
10. The printed wiring board semiconductor package of claim 9 , wherein the first and second inner layer panel capacitors are selected from the group consisting of ceramic capacitors, thick film capacitors, thin film capacitors, capacitors comprising a material having a high dielectric constant, and combinations of these.
11. The printed wiring board semiconductor package of claim 9 , wherein the printed wiring board semiconductor package possesses reduced impedance in a range of targeted frequency between about 5×10 7 Hertz and about 3×10 9 Hertz.
12. The printed wiring board semiconductor package of claim 9 , wherein the first and second inner layer panel capacitors each comprise a singulated, fired-on-foil capacitor.
13. The printed wiring board semiconductor package of claim 12 , wherein the first and second inner layer panel capacitors are located in adjacent inner layer panels such that no other capacitors are located between the first and second inner layer panel capacitors.
14. A device for reducing impedance at a targeted frequency, the device comprising:
a printed wiring board semiconductor package;
a semiconductor attached thereto and projecting a die shadow onto the printed wiring board semiconductor package,
wherein the printed wiring board package includes a first inner layer panel stacked on and adjacent to a second inner layer panel, wherein the first inner layer panel comprises a first inner layer panel capacitor, wherein the second inner layer panel comprises a second inner layer panel capacitor, and wherein the first inner layer panel capacitor includes an area differing from that of the second inner layer panel capacitor;
wherein the first and second inner layer panels are laminated together in overlying succession such that the first inner layer panel capacitor is at a differing vertical distance from the semiconductor than the second inner layer panel capacitor; and
wherein at least a part of each of the first and second inner layer panel capacitors lies within the die shadow; and
a conductive via interconnecting the first and second inner layer capacitors to the semiconductor.
15. The device of claim 14 , wherein the first and second inner layer panel capacitors are selected from the group consisting of ceramic capacitors, thick film capacitors, thin film capacitors, capacitors comprising a material having a high dielectric constant, and combinations of these.
16. The device of claim 14 , wherein the printed wiring board semiconductor package possesses reduced impedance in a range of targeted frequency between about 5×10 7 Hertz and about 3×10 9 Hertz.
17. The device of claim 14 , wherein the first and second inner layer panel capacitors each comprise a singulated, fired-on-foil capacitor.
18. The device of claim 17 , wherein the first and second inner layer panel capacitors are located in adjacent inner layer panels such that no other capacitors are located between the first and second inner layer panel capacitors.