Replacement gate electrode with planar work function material layers
In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function material portion to form a gate structure that enhances performance of a replacement gate field effect transistor.
1. A method of forming a semiconductor structure comprising:
forming a gate cavity laterally surrounded by a planarization dielectric layer on a semiconductor substrate, wherein a top surface of said semiconductor substrate is exposed at a bottom of said gate cavity;
forming a gate dielectric layer in said gate cavity;
forming at least one planar work function material portion having a topmost surface that is recessed from a topmost surface of said planarization dielectric layer on said gate dielectric layer in said gate cavity, wherein each of said at least one planar work function material portion is formed by anisotropically depositing a work function metal material layer that provides vertical portions of the work function metal material layer having a lesser thickness than a horizontal portion of the work function metal material layer so that said horizontal portion of said work function metal material layer has a thickness that is at least three times a thickness of said vertical portion of said work function metal material layer, wherein forming the at least one planar work function material portion further includes removing said vertical portions of said work function metal material layer with an isotropic etch so the horizontal portion of the work function metal material layer remains to provide the at least one planar work function material portion; and
filling said gate cavity with a metal layer contacting said at least one planar work function material portion.
2. The method of claim 1 , wherein each of said at least one planar work function material portion has a uniform thickness between one inner vertical sidewall of said gate dielectric layer and another inner vertical sidewall of said gate dielectric layer.
3. The method of claim 1 , wherein said work function metal material layer is deposited by collimated physical vapor deposition (PVD), radio frequency physical vapor deposition (RFPVD) sputtering, or constant voltage substrate bias.
4. The method of claim 1 , wherein said isotropic etch is a wet etch or gas phase etch.
5. The method of claim 1 , further comprising:
forming a disposable gate structure on said semiconductor substrate prior to forming said planarization dielectric layer; and
planarizing said planarization dielectric layer, wherein a topmost surface of a disposable gate cap dielectric is coplanar with said topmost surface of said planarization dielectric layer after said planarizing, and said gate cavity is formed by removing said disposable gate structure.
6. The method of claim 1 , further comprising planarizing said gate dielectric layer and said metal layer, where a remaining portion of said gate dielectric layer forms a gate dielectric and a remaining portion of said metal layer forms a metal portion, and topmost surfaces of said gate dielectric and said metal portion are coplanar with said topmost surface of said planarization dielectric layer.
7. The method of claim 6 , wherein said gate dielectric is formed as a U-shaped gate dielectric including a horizontal gate dielectric portion and a vertical gate dielectric portion, wherein said vertical gate dielectric portion contiguously extends from said horizontal gate dielectric portion to said topmost surface of said planarization dielectric layer.
8. The method of claim 6 , wherein said topmost surface of said at least one planar work function material portion is a horizontal surface that extends from one inner sidewall of said gate dielectric to another inner sidewall of said gate dielectric.
9. The method of claim 6 , wherein said at least one planar work function material portion comprises a stack of a planar work function material portion and another planar work function material portion, said planar work function material portion comprises a metallic material selected from Pt, Rh, Ir, Ru, Cu, Os, Be, Co, Pd, Te, Cr, Ni, TiN, a stack thereof, a conductive oxide thereof, a conductive nitride thereof, an alloy thereof, and a combination thereof, and said another planar work function material portion comprises another metallic material selected from Hf, Ti, Zr, Cd, La, Tl, Yb, Al, Ce, Eu, Li, Pb, Tb, Bi, In, Lu, Nb, Sm, V, Zr, Ga, Mg, Gd, Y, TiAl, TaN, a stack thereof, a conductive oxide thereof, a conductive nitride thereof, an alloy thereof, and a combination thereof.
10. The method of claim 1 , wherein the horizontal portion of said work function metal material layer has a thickness that is at least four times a thickness of said vertical portion of said work function metal material layer.
11. The method of claim 1 , wherein the horizontal portion of said work function metal material layer has a thickness that is up to five times a thickness of said vertical portion of said work function metal material layer.
12. A method of forming a semiconductor structure comprising:
forming a gate cavity laterally surrounded by a planarization dielectric layer on a semiconductor substrate, wherein a top surface of said semiconductor substrate is exposed at a bottom of said gate cavity;
forming a gate dielectric layer in said gate cavity;
forming at least one planar work function material portion having a topmost surface that is recessed from a topmost surface of said planarization dielectric layer on said gate dielectric layer in said gate cavity, wherein each of said at least one planar work function material portion comprises a metallic material selected from Pt, Rh, Ir, Ru, Cu, Os, Be, Co, Pd, Te, Cr, Ni, TiN, Hf, Ti, Zr, Cd, La, Tl, Yb, Al, Ce, Eu, Li, Pb, Tb, Bi, In, Lu, Nb, Sm, V, Zr, Ga, Mg, Gd, Y, TiAl, TaN, a stack thereof, a conductive oxide thereof, a conductive nitride thereof, an alloy thereof, and a combination thereof, wherein each of said at least one planar work function material portion is formed by anisotropically depositing a work function metal material layer that provides vertical portions of the work function metal material layer having a lesser thickness than a horizontal portion of the work function metal material layer, wherein forming the at least one planar work function material portion further includes removing said vertical portions of said work function metal material layer with an isotropic etch so the horizontal portion of the work function metal material layer remains to provide the at least one planar work function material portion; and
filling said gate cavity with a metal layer contacting said at least one planar work function material portion.