Semicondcutor device comprising transistor
View Patent ↗The present invention provides a transistor and a method for forming the same. The method includes: providing a semiconductor substrate having a semiconductor layer formed thereon, the semiconductor layer and the semiconductor substrate having different crystal orientations; forming a dummy gate structure on the semiconductor layer; forming a source region and a drain region in the semiconductor substrate and the semiconductor layer and at opposite sides of the dummy gate structure; forming an interlayer dielectric layer on the semiconductor layer, which is substantially flush with the dummy gate structure; removing the dummy gate structure and the semiconductor layer beneath the dummy gate structure, forming an opening in the interlayer dielectric layer and the semiconductor layer, the semiconductor substrate being exposed at a bottom of the opening; forming a metal gate structure in the opening. Saturation current of the transistor is raised, and performance of a semiconductor device is promoted.
1. A transistor, comprising:
a semiconductor substrate having a semiconductor layer formed thereon, the semiconductor layer and the semiconductor substrate having different crystal orientations;
an interlayer dielectric layer formed on the semiconductor layer;
an opening formed through the interlayer dielectric layer and through the semiconductor layer having a portion of the semiconductor layer in the opening, the semiconductor substrate being exposed at a bottom of the opening;
a metal gate structure formed in the opening;
a source region formed in the semiconductor layer and the semiconductor substrate; and
a drain region formed in the semiconductor layer and the semiconductor substrate, the source region and the drain region being respectively at opposite sides of the metal gate structure, wherein the portion of the semiconductor layer in the opening is between the source region and the drain region, and has the different crystal orientation than the underlying semiconductor substrate.
2. The transistor according to claim 1 , wherein the transistor is an NMOS transistor, the semiconductor substrate has crystal orientation (100), and the semiconductor layer has crystal orientation (110).
3. The transistor according to claim 1 , wherein the transistor is a PMOS transistor, the semiconductor substrate has crystal orientation (110), and the semiconductor layer has crystal orientation (100).
4. The transistor according to claim 1 , wherein the semiconductor layer has thickness in a range of 3 nm to 30 nm.
5. The transistor according to claim 1 , further comprising:
lightly doped regions formed in the semiconductor substrate and the portion of the semiconductor layer in the opening, and at the opposite sides of the metal gate structure between the source region and the drain region.
6. The transistor according to claim 5 , further comprising:
an epitaxial layer formed between the metal gate structure and the semiconductor substrate exposed at the bottom of the opening, and between the source region and the drain region, the epitaxial layer having a same crystal orientation with the underlying semiconductor substrate exposed at the bottom of the opening and being flush with the portion of the semiconductor layer in the opening.
7. The transistor according to claim 6 , wherein the epitaxial layer is made of silicon germanium, and mass concentration of the germanium in the silicon germanium is ranged from 4% to 40%.
8. The transistor according to claim 6 , wherein the epitaxial layer has defect absorbing ions which are used for absorbing defects in a channel region.
9. The transistor according to claim 8 , wherein the defect absorbing ions are fluoride ions or nitrogen ions.