Reconfigurable logic fabrics for integrated circuits and systems and methods for configuring reconfigurable logic fabrics

1. An apparatus, comprising:

an asynchronous memory block having an asynchronous input and an asynchronous output;

a pair of asynchronous reconfigurable logic blocks, one of the pair coupled to the asynchronous input and the other one of the pair coupled to the asynchronous output; and

a pair of input/output (I/O) blocks coupled to corresponding ones of the pair of asynchronous reconfigurable logic blocks, the pair of I/O blocks selectably configurable to provide synchronous I/O banks and/or asynchronous I/O banks.

2. The apparatus of claim 1 , wherein the asynchronous memory block is configured to operate, at least in part, as a circular buffer.

3. The apparatus of claim 1 , wherein the pair of I/O blocks are configured to provide one of a bundled-data interface to implement an asynchronous handshake protocol or a serial link to implement asynchronous communication.

4. The apparatus of claim 1 wherein at least one of the pair of I/O blocks comprises a converter unit to provide synchronous to asynchronous signal conversion, or asynchronous to synchronous signal conversion.

5. The apparatus of claim 1 , wherein the asynchronous memory block comprises a reprogrammable number of ports.

6. The apparatus of claim 1 , configured as a field programmable gate array.

7. The apparatus of claim 1 , further comprising:

a programmable asynchronous multiplier block coupled to the asynchronous memory block.

8. The apparatus of claim 1 , further comprising:

an interconnecting grid; and

a programmable interconnect element to couple the asynchronous memory block to the interconnecting grid.

9. The apparatus of claim 8 , wherein the programmable interconnect element s asynchronous and pipelined.

10. The apparatus of claim 8 , wherein the interconnecting grid comprises switch boxes at intersecting portions.

11. The apparatus of claim 1 , wherein at least one of the asynchronous reconfigurable logic blocks comprise only asynchronous logic circuits.

12. The apparatus of claim 1 , wherein at least one of the asynchronous reconfigurable logic blocks comprise programmable logic clusters.

13. The apparatus of claim 1 , wherein at least one of the asynchronous reconfigurable logic blocks comprise circuit elements to provide wide AND, wide OR, and/or sum-of-products operations.

14. The apparatus of claim 1 , wherein at least one of the asynchronous reconfigurable logic blocks comprise a multi-input lookup table.

15. The apparatus of claim 1 , wherein at least one of the asynchronous reconfigurable logic blocks comprise a multiplexer.

16. The apparatus of claim 1 , wherein at least one of the asynchronous reconfigurable logic blocks comprise dedicated early-out carry chain circuitry.

17. The apparatus of claim 1 , wherein at least one of the asynchronous reconfigurable logic blocks is configured to implement state-holding computations.

18. A method, comprising:

synchronously communicating information with at least one of a pair of input/output (I/O) blocks, a first one of the pair of blocks coupled to a first one of a pair of asynchronous reconfigurable logic blocks, and a second one of the pair of I/O blocks coupled to a second one of the pair of asynchronous reconfigurable logic blocks, the pair of I/O blocks selectably configurable to provide synchronous I/O banks and/or asynchronous I/O banks; and

asynchronously accessing a memory to store the information in an asynchronous memory block coupled to the pair of asynchronous reconfigurable logic blocks.

19. The method of claim 18 , further comprising:

operating at least a portion of the asynchronous memory block as a circular buffer.

20. The method of claim 18 , further comprising:

generating tokens, from sources within the memory, to supply unused inputs in logic clusters forming part of at least one of the pair of asynchronous reconfigurable logic blocks.