IP Library Granted Patent US 8,580,696
Granted Patent B2
US 8,580,696 · App. 11/829,581 · Granted Nov 12, 2013

Systems and methods for detecting watermark formations on semiconductor wafers

Inventors: Kiyoshi Mori (San Antonio, TX); Shu Ikeda (Austin, TX); Gabriel Gebara (Austin, TX)
Assignee: Abound Limited
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Quick Facts
Patent No.
US 8,580,696
App. No.
11/829,581
Granted
Nov 12, 2013
Kind
B2
Abstract

Systems and methods for detecting watermark formations on semiconductor wafers are described. In one embodiment, a method comprises providing a semiconductor wafer having at least one watermark sensitive region fabricated thereon, subjecting the wafer to a wet processing step, enhancing a susceptibility to detection of at least one watermark formation created on the at least one watermark sensitive region, and detecting the at least one watermark formation. In another embodiment, a method comprises growing a first oxide layer on a surface of a semiconductor wafer, patterning a watermark sensitive structure on the first oxide layer, depositing a silicon layer over the first oxide layer, doping a region of the silicon layer over the watermark sensitive structure with an impurity to create a watermark sensitive region that is prone to retaining watermark formations as result of a wet processing step, and growing a second oxide layer over the silicon layer.

Claims (13)

1. A method comprising:

growing a first oxide layer on a surface of a semiconductor wafer;

patterning a first watermark sensitive structure on the first oxide layer;

depositing a silicon layer over the first oxide layer;

doping a first region of the silicon layer over the first watermark sensitive structure with an impurity under a first condition to create a first watermark sensitive region that is prone, to a first degree, to retaining watermark formations as result of a wet processing step; and

growing a second oxide layer over the silicon layer.

2. The method of claim 1 , further comprising:

patterning a second watermark sensitive structure on the first oxide layer; and

doping a second region of the silicon layer over the second watermark sensitive structure with an impurity under a second condition to create a second watermark sensitive region that is prone, to a second degree, to retaining watermark formations as result of the wet processing step.

3. The method of claim 1 , further comprising:

subjecting the semiconductor wafer to the wet processing step;

enhancing a susceptibility to detection of at least one watermark formation created on at least one of the first and second watermark sensitive regions; and

detecting the at least one watermark formation.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2015
From: ABOUND (BVI) LIMITED
To: SUZHOU TECHNOLOGY INSTITUTE FOR NANOTECH INDUSTRY
Reel/Frame 035768/0010 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 20, 2013
From: SVTC TECHNOLOGIES, LLC
To: ABOUND LIMITED
Reel/Frame 031045/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2009
From: SEMATECH, INC.
To: SVTC TECHNOLOGIES, INC.
Reel/Frame 022611/0122 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2007
From: MORI, KIYOSHI; IKEDA, SHU; GEBARA, GABRIEL
To: SEMATECH, INC.
Reel/Frame 019747/0696 →
Continuity (1)
Related Publication 20090028422A1 · Jan 29, 2009