Semiconductor device including a memory
Plural kinds of thin film transistors having different film thicknesses of semiconductor layers are provided over a substrate having an insulating surface. A channel formation region of semiconductor layer in a thin film transistor for which high speed operation is required is made thinner than a channel formation region of a semiconductor layer of a thin film transistor for which high withstand voltage is required. A gate insulating layer of the thin film transistor for which high speed operation is required may be thinner than a gate insulating layer of the thin film transistor for which high withstand voltage is required.
1. A semiconductor device comprising:
a memory including a memory cell array comprising a first thin film transistor and a driver circuit portion comprising a second thin film transistor,
wherein the memory cell array and the driver circuit portion are provided over a substrate having an insulating surface,
wherein the first thin film transistor comprises:
a first gate electrode layer;
a first semiconductor layer including a first source region, a first drain region, and a first channel formation region; and
a first gate insulating layer,
wherein the second thin film transistor comprises:
a second gate electrode layer;
a second semiconductor layer including a second source region, a second drain region, and a second channel formation region that is thinner than the first channel formation region; and
a second gate insulating layer that is thinner than the first gate insulating layer,
wherein the memory includes a booster circuit over the substrate, and
wherein the booster circuit includes a third thin film transistor which includes a third gate electrode layer; a third semiconductor layer including a third source region, a third drain region, and a third channel formation region that is thicker than the second channel formation region of the second semiconductor layer; and a third gate insulating layer.
2. The semiconductor device according to claim 1 , wherein insulating layers having a sidewall structure are provided on side surfaces of the first gate electrode layer and the second gate electrode layer.
3. The semiconductor device according to claim 1 , wherein silicides are provided in surface portions of the first source region, the first drain region, the second source region, and the second drain region.
4. The semiconductor device according to claim 1 , wherein insulating layers having a sidewall structure are provided on side surfaces of the first semiconductor layer and the second semiconductor layer.
5. The semiconductor device according to claim 1 ,
wherein a power supply circuit is provided over the substrate having the insulating surface, and
wherein the power supply circuit includes a third thin film transistor which includes a third gate electrode layer; a third semiconductor layer including a third source region, a third drain region, and a third channel formation region that is thicker than the second channel formation region of the second semiconductor layer; and a third gate insulating layer.
6. A semiconductor device comprising:
a memory including a memory cell array comprising a first thin film transistor and a driver circuit portion comprising a second thin film transistor,
wherein the memory cell array and the driver circuit portion are provided over a substrate having an insulating surface,
wherein the first thin film transistor comprises:
a first gate electrode layer;
a first semiconductor layer including a first source region, a first drain region, and a first channel formation region; and
a first gate insulating layer,
wherein the second thin film transistor comprises:
a second gate electrode layer;
a second semiconductor layer including a second source region, a second drain region, and a second channel formation region that is thinner than the first channel formation region;
a second gate insulating layer that is thinner than the first gate insulating layer; and
wherein the second channel formation region is thinner than the second source region and the second drain region,
wherein the memory includes a booster circuit over the substrate, and
wherein the booster circuit includes a third thin film transistor which includes a third gate electrode layer; a third semiconductor layer including a third source region, a third drain region, and a third channel formation region that is thicker than the second channel formation region of the second semiconductor layer; and a third gate insulating layer.
7. The semiconductor device according to claim 6 , wherein insulating layers having a sidewall structure are provided on side surfaces of the first gate electrode layer and the second gate electrode layer.
8. The semiconductor device according to claim 6 , wherein silicides are provided in surface portions of the first source region, the first drain region, the second source region, and the second drain region.
9. The semiconductor device according to claim 6 , wherein insulating layers having a sidewall structure are provided on side surfaces of the first semiconductor layer and the second semiconductor layer.
10. The semiconductor device according to claim 6 ,
wherein a power supply circuit is provided over the substrate having the insulating surface, and
wherein the power supply circuit includes a third thin film transistor which includes a third gate electrode layer; a third semiconductor layer including a third source region, a third drain region, and a third channel formation region that is thicker than the second channel formation region of the second semiconductor layer; and a third gate insulating layer.