IP Library Granted Patent US 8,582,267
Granted Patent B2
US 8,582,267 · App. 12/718,526 · Granted Nov 12, 2013

System and method to limit in-rush current

Inventor: John Pellegrino (Westford, MA)
Assignee: The Charles Stark Draper Laboratory, Inc.
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Quick Facts
Patent No.
US 8,582,267
App. No.
12/718,526
Granted
Nov 12, 2013
Kind
B2
Abstract

An in-rush current limiting system has a fast response time so that it can be used with power supplies that turn on and off rapidly. The system dissipates very little power during the normal mode of operation. This is achieved, in various embodiments, by connecting a regulator in series with a load capacitance and in parallel with the system load.

Claims (37)

1. An in-rush current-limiting system, comprising:

a power source comprising first and second terminals;

a load connected to the first and second terminals of the power source without an active component connected in series therebetween; and

in-rush current-limiting circuitry comprising:

a load capacitor;

a regulator connected in series with the load capacitor, a series combination of the regulator and the load capacitor being connected in parallel to the load; and

a feedback circuit for sensing a current flowing through the load capacitor while the regulator is ON and for controlling the regulator while the regulator is maintained ON based on, at least in part, the sensed current.

2. The in-rush current limiting system of claim 1 , wherein the regulator is a transistor.

3. The in-rush current limiting system of claim 2 , wherein the transistor is a field-effect transistor.

4. The in-rush current limiting system of claim 2 , wherein the transistor is a bipolar junction transistor.

5. The in-rush current limiting system of claim 1 , wherein the feedback circuit comprises

a current-sensing element;

an amplifier; and

a biasing circuit.

6. The in-rush current limiting system of claim 5 , wherein the current-sensing element is a resistor.

7. The in-rush current limiting system of claim 5 , wherein the amplifier is a transistor.

8. The in-rush current limiting system of claim 5 , wherein the amplifier is an integrated circuit.

9. The in-rush current limiting system of claim 5 , wherein the biasing circuit comprises first and second resistors.

10. The in-rush current limiting system of claim 5 , wherein the biasing circuit comprises current-source circuitry.

11. A method of limiting in-rush current in a circuit having a load, a load capacitor, and a power source comprising first and second terminals, the method comprising the steps of:

supplying, from the power source, source current comprising in-rush capacitor current and load current, the load current being supplied to the load, the load connected to the first and second terminals of the power source without an active component connected in series therebetween;

sensing, in a feedback circuit and while a regulator is ON, the in-rush capacitor current flow in the regulator, the regulator connected in series with the load capacitor, a series combination of the regulator and the load capacitor being connected in parallel to the load; and

in response to the sensed in-rush capacitor current flow, adjusting an impedance of the regulator while the regulator is maintained ON.

12. The method of claim 11 , further comprising the steps of:

initially setting the regulator impedance to a low value; and

initially setting the feedback circuit to an off mode.

13. The method of claim 11 , further comprising the steps of:

setting the feedback circuit to an on mode when the sensed in-rush capacitor current flow exceeds a predetermined threshold; and

in response, setting the regulator impedance to a high value.

14. The method of claim 11 , further comprising the steps of:

setting the feedback circuit to an off mode when the sensed in-rush capacitor current flow is less than a predetermined threshold; and

in response, setting the regulator impedance to a low value.

15. A method of limiting in-rush current in a circuit having an in-rush capacitor and a system load, the method comprising the steps of:

connecting first and second terminals of a power source to the system load without connecting an active component in series therebetween;

connecting a regulator in series with the in-rush capacitor;

connecting a series combination of the regulator and the in-rush capacitor in parallel with the system load; and

controlling the regulator while maintaining the regulator ON using feedback responsive to current flowing through the in-rush capacitor and sensed while the regulator is ON.

Assignments (2)
CONFIRMATORY LICENSE Recorded May 12, 2014
From: CHARLES STARK DRAPER LAB, INC.
To: NAVY, U.S. NAVY AS REPRESENTED BY THE SECRETARY OF THE
Reel/Frame 032918/0770 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 10, 2010
From: PELLEGRINO, JOHN
To: THE CHARLES STARK DRAPER LABORATORY, INC.
Reel/Frame 024058/0592 →
Continuity (1)
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