Dual-gate normally-off nitride transistors

1. A dual-gate normally-off nitride transistor comprising:

a first gate structure formed between a source electrode and a drain electrode for controlling a normally-off channel region of the dual-gate normally-off nitride transistor, said first gate structure covers a first area of said normally-off channel region; and

a second gate structure formed between the first gate structure and the drain electrode for modulating a normally-on channel region underneath the second gate structure, said second gate structure covers a second area of said normally-on channel region;

wherein the magnitude of the threshold voltage of the second gate structure is smaller than the drain-to-source punch-through voltage of the first gate structure for proper operation of the dual-gate normally-off nitride transistor, the length of said second gate structure is longer than the length of said first gate structure.

2. The dual-gate normally-off nitride transistor of claim 1 , wherein the first gate structure comprises a gate structure formed using gate recess, plasma treatment, surface potential modulation, polarization engineering, or p-type gate material.

3. The dual-gate normally-off nitride transistor of claim 1 , wherein the first gate structure is positioned between the source electrode and the drain electrode on a region of a barrier layer.

4. The dual-gate normally-off nitride transistor of claim 1 , wherein the second gate structure is positioned between the first gate structure and the drain electrode.

5. The dual-gate normally-off nitride transistor of claim 3 , wherein the barrier layer comprises In y Al x Ga 1-x-y N (0≦x,y≦1, x+y=1).

6. The dual-gate normally-off nitride transistor of claim 1 , wherein the source electrode and the drain electrode are in contact with a channel layer.

7. The dual-gate normally-off nitride transistor of claim 6 , wherein the channel layer is positioned on a substrate.

8. The dual-gate normally-off nitride transistor of claim 1 , wherein the second gate structure comprises an independent bias, connected to the source electrode or connected to the first gate structure.

9. The dual-gate normally-off nitride transistor of claim 1 , wherein the second gate structure is integrated with the first gate structure when the second gate structure needs to be connected to the first gate structure.

10. The dual-gate normally-off nitride transistor of claim 1 further comprising a dielectric layer being positioned on a thin AlGa(In)N barrier layer.

11. A method of forming a dual-gate normally-off nitride transistor comprising:

forming a first gate structure between a source electrode and a drain electrode for controlling a normally-off channel region of the dual-gate normally-off nitride transistor, said first gate structure covers a first area of said normally-off channel region; and

forming a second gate structure between the first gate structure and the drain electrode for modulating a normally-on channel region underneath the second gate structure, said second gate structure covers a second area of said normally-on channel region, wherein the magnitude of the threshold voltage of the second gate structure is smaller than the drain-to-source punch-through voltage of the first gate structure for proper operation of the dual-gate normally-off nitride transistor, the length of said second gate structure is longer than the length of said first gate structure.

12. The method of claim 11 , wherein the first gate structure comprises a gate structure formed using gate recess, plasma treatment, surface potential modulation, polarization engineering, or p-type gate material.

13. The method of claim 11 , wherein the first gate structure is positioned between the source electrode and the drain electrode on a region of a barrier layer.

14. The method of claim 11 , wherein the second gate structure is positioned between the first gate structure and the drain electrode.

15. The method of claim 13 , wherein the barrier layer comprises In y Al x Ga 1-x-y N (0≦x,y≦1, x+y=1).

16. The method of claim 11 , wherein the source electrode and drain electrode are in contact with a channel layer.

17. The method of claim 16 , wherein the channel layer is positioned on a substrate.

18. The method of claim 11 , wherein the second gate structure comprises an independent bias, connected to the source electrode or connected to the first gate structure.

19. The method of claim 11 , wherein the second gate structure is integrated with the first gate structure when the second gate structure needs to be connected to the first gate structure.

20. The method of claim 11 further comprising a dielectric layer being positioned on a thin AlGa(In)N barrier layer.

21. A transistor-based power device comprising:

a first gate structure formed between a source electrode and a drain electrode for controlling a normally-off channel region of the dual-gate normally-off nitride transistor, said first gate structure covers a first area of said normally-off channel region; and

a second gate structure formed between the first gate structure and the drain electrode for modulating a normally-on channel region underneath the second gate structure said second gate structure covers a second area of said normally-on channel region;

wherein the magnitude of the threshold voltage of the second gate structure is smaller than the drain-to-source punch-through voltage of the first gate structure for proper operation of the dual-gate normally-off nitride transistor, the length of said second gate structure is longer than the length of said first gate structure.