IP Library › Granted Patent US 8,612,680
Granted Patent B1
US 8,612,680 · App. 12/828,111 · Granted Dec 17, 2013

Data caching system and method

Inventors: Kiran Madnani (Framingham, MA); Randall H. Shain (Wrentham, MA); David W. DesRoches (Methuen, MA)
Assignee: EMC Corporation
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Quick Facts
Patent No.
US 8,612,680
App. No.
12/828,111
Filed
Jun 30, 2010
Granted
Dec 17, 2013
Kind
B1
Examiner
YU, JAE UN
Art Unit
2185
USPC
711/114
Abstract

A system, computer program product, and computer-implemented method for defining a data stripe that spans one or more of N data storage devices and one or more of M erasure code devices. The one or more N data storage devices and the one or more M erasure code devices are included within a data storage system. A data chunk to be written to the data storage system is received. At least a portion of the data chunk is written to the portion of the data stripe that spans the one or more N data storage devices. Each of the N data storage devices and the M erasure code devices is included within a unique server computer.

Claims (50)

1. A data caching system comprising:

a data storage system including:

N data storage devices, and

M erasure code devices;

at least one processor;

at least one memory architecture coupled with the at least one processor;

a first software module executed on the at least one processor and the at least one memory architecture, wherein the first software module is configured to perform operations including defining a data stripe that spans one or more of the N data storage devices and one or more of the M erasure code devices, including defining a plurality of data stripes that each span one or more of the N data storage devices and one or more of the M erasure code devices;

a second software module executed on the at least one processor and the at least one memory architecture, wherein the second software module is configured to perform operations including receiving a data chunk to be written to the data storage system, wherein the data chunk received is larger in size than the capacity of the data stripe; and

a third software module executed on the at least one processor and the at least one memory architecture, wherein the third software module is configured to perform operations including writing at least a portion of the data chunk to the portion of the data stripe that spans the one or more N data storage devices, including writing at least a portion of the data chunk to the portion of each of the plurality of data stripes that spans the one or more N data storage devices;

wherein each of the N data storage devices and the M erasure code devices is included within a unique server computer.

2. The data caching system of claim 1 wherein the data stripe spans all of the N data storage devices, and wherein writing at least a portion of the data chunk to the portion of the data stripe that spans the one or more N data storage devices includes:

writing at least a portion of the data chunk to the portion of the data stripe that spans all of the N data storage devices.

3. The data caching system of claim 1 wherein the data stripe spans one of the N data storage devices, and wherein writing at least a portion of the data chunk to the portion of the data stripe that spans the one or more N data storage devices includes:

writing at least a portion of the data chunk to the portion of the data stripe that spans one of the N data storage devices.

4. The data caching system of claim 1 further comprising:

a fourth software module executed on the at least one processor and the at least one memory architecture, wherein the fourth software module is configured to perform operations including:

generating erasure code data based, at least in part, upon the data chunk to be written to the data storage system, and

writing at least a portion of the erasure code data to the portion of the data stripe that spans the one or more M erasure code devices.

5. The data caching system of claim 4 wherein the erasure code data includes parity data.

6. The data caching system of claim 1 further comprising a fifth software module executed on the at least one processor and the at least one memory architecture, wherein the fifth software module is configured to perform operations including:

temporarily storing at least a portion of the data chunk in a high availability fashion prior to writing at least a portion of the data chunk to the portion of the data stripe that spans the one or more N data storage devices.

7. A computer program product residing on a non-transitory computer readable medium having a plurality of instructions stored thereon that, when executed by a processor, cause the processor to perform operations comprising:

defining a data stripe that spans one or more of N data storage devices and one or more of M erasure code devices, including defining a plurality of data stripes that each span one or more of the N data storage devices and one or more of the M erasure code devices, wherein the one or more N data storage devices and the one or more M erasure code devices are included within a data storage system;

receiving a data chunk to be written to the data storage system, wherein the data chunk received is larger in size than the capacity of the data stripe; and

writing at least a portion of the data chunk to the portion of the data stripe that spans the one or more N data storage devices, including writing at least a portion of the data chunk to the portion of each of the plurality of data stripes that spans the one or more N data storage devices;

wherein each of the N data storage devices and the M erasure code devices is included within a unique server computer.

8. The computer program product of claim 7 wherein the data stripe spans all of the N data storage devices, and wherein the instructions for writing at least a portion of the data chunk to the portion of the data stripe that spans the one or more N data storage devices include instructions for:

writing at least a portion of the data chunk to the portion of the data stripe that spans all of the N data storage devices.

9. The computer program product of claim 7 wherein the data stripe spans one of the N data storage devices, and wherein the instructions for writing at least a portion of the data chunk to the portion of the data stripe that spans the one or more N data storage devices include instructions for:

writing at least a portion of the data chunk to the portion of the data stripe that spans one of the N data storage devices.

10. The computer program product of claim 7 further comprising instructions for:

generating erasure code data based, at least in part, upon the data chunk to be written to the data storage system, and

writing at least a portion of the erasure code data to the portion of the data stripe that spans the one or more M erasure code devices.

11. The computer program product of claim 10 wherein the erasure code data includes parity data.

12. The computer program product of claim 7 further comprising instructions for:

temporarily storing at least a portion of the data chunk in a high availability fashion prior to writing at least a portion of the data chunk to the portion of the data stripe that spans the one or more N data storage devices.

13. A computer-implemented method comprising:

defining a data stripe that spans one or more of N data storage devices and one or more of M erasure code devices, including defining a plurality of data stripes that each span one or more of the N data storage devices and one or more of the M erasure code devices, wherein the one or more N data storage devices and the one or more M erasure code devices are included within a data storage system;

receiving a data chunk to be written to the data storage system, wherein the data chunk received is larger in size than the capacity of the data stripe; and

writing at least a portion of the data chunk to the portion of the data stripe that spans the one or more N data storage devices, including writing at least a portion of the data chunk to the portion of each of the plurality of data stripes that spans the one or more N data storage devices;

wherein each of the N data storage devices and the M erasure code devices is included within a unique server computer.

14. The computer-implemented method of claim 13 wherein the data stripe spans all of the N data storage devices, and wherein writing at least a portion of the data chunk to the portion of the data stripe that spans the one or more N data storage devices includes:

writing at least a portion of the data chunk to the portion of the data stripe that spans all of the N data storage devices.

15. The computer-implemented method of claim 13 wherein the data stripe spans one of the N data storage devices, and wherein writing at least a portion of the data chunk to the portion of the data stripe that spans the one or more N data storage devices includes:

writing at least a portion of the data chunk to the portion of the data stripe that spans one of the N data storage devices.

16. The computer-implemented method of claim 13 further comprising:

generating erasure code data based, at least in part, upon the data chunk to be written to the data storage system, and

writing at least a portion of the erasure code data to the portion of the data stripe that spans the one or more M erasure code devices.

17. The computer-implemented method of claim 16 wherein the erasure code data includes parity data.

18. The computer-implemented method of claim 13 further comprising: temporarily storing at least a portion of the data chunk in a high availability fashion prior to writing at least a portion of the data chunk to the portion of the data stripe that spans the one or more N data storage devices.

Assignments (10)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (045455/0001) Recorded May 20, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO ASAP SOFTWARE EXPRESS, INC.); DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC CORPORATION (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MAGINATICS LLC); EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.); SCALEIO LLC
Reel/Frame 061753/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (040136/0001) Recorded Apr 26, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO ASAP SOFTWARE EXPRESS, INC.); DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC CORPORATION (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MAGINATICS LLC); EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.); SCALEIO LLC
Reel/Frame 061324/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 3, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL USA L.P.; DELL INTERNATIONAL, L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; WYSE TECHNOLOGY L.L.C.
Reel/Frame 058216/0001 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 29, 2016
From: EMC CORPORATION
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 040203/0001 →
SECURITY AGREEMENT Recorded Sep 21, 2016
From: ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; SPANNING CLOUD APPS LLC; WYSE TECHNOLOGY L.L.C.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 040136/0001 →
SECURITY AGREEMENT Recorded Sep 21, 2016
From: ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; SPANNING CLOUD APPS LLC; WYSE TECHNOLOGY L.L.C.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 040134/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2010
From: MADNANI, KIRAN; SHAIN, RANDALL H.; DESROCHES, DAVID W.
To: EMC CORPORATION
Reel/Frame 024974/0064 →